Embedded Files
Generate a clock signal at 2Hz duty cycle=25%.
Generate a clock signal at 2Hz duty cycle=25%.
The Nexys4 DDR board features a built-in oscillator that generates a 100 MHz clock signal. In most design scenarios, you will need to divide this high-frequency clock to obtain a lower operating frequency suitable for your circuit. This example demonstrates how to leverage a counter design to generate a repeating sequence and compare it against a user-defined parameter. This comparison determines the duty cycle of the output signal produced by the frequency divider circuit.
Prerequisites
Prerequisites
Oscillators/Clocks on the Nexys4 DDR
Oscillators/Clocks on the Nexys4 DDR
The Nexys4 DDR board includes a single 100 MHz crystal oscillator connected to pin E3 (E3 is a MRCC input on bank 35).
(source)
System architecture
System architecture
Recommended Dev File Management
Recommended Dev File Management
RTL Reference
RTL Reference
RTL Structure
RTL Structure
Testbench Reference
Testbench Reference
Simulation Example
Simulation Example
The simulation results demonstrate the following behavior:
The output signal has a period of 20 × 10ns = 200ns. The duty cycle of the output signal is calculated as 40ns / 200ns = 25%, indicating that the signal is high for 25% of the period.
Note: Exercise caution when specifying the parameter values in the simulator, as they directly impact the observed waveforms and duty cycle calculations.
Constraint File Reference
Constraint File Reference
Demonstration
Demonstration
Page updated
Report abuse