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Let's begin with the design of a 4-bit counter that should function similarly to the 74191 counter integrated circuit, repeatedly generating a 4-bit binary sequence.
RTL Reference for 4-bit binary sequence generator
RTL Reference for 4-bit binary sequence generator
Testbench Reference for 4-bit binary sequence generator
Testbench Reference for 4-bit binary sequence generator
Simulation results (4-bit binary sequence generator)
Simulation results (4-bit binary sequence generator)
The built-in oscillator on the FPGA board has a period of 10 nanoseconds. By implementing a counter that increments from 0 to f and then repeats, a new sequence is generated with a period of 100 nanoseconds (16 counts × 10 ns per count). This process effectively divides the input clock frequency by a factor of 16, resulting in a lower output frequency.
Incorporate a condition that constrains the counter's value to remain within the range of 0 to 9.
RTL Reference for Count-10 counter
RTL Reference for Count-10 counter
Testbench Reference for Count-10 counter
Testbench Reference for Count-10 counter
Simulation results (Count-10 counter)
Simulation results (Count-10 counter)
The built-in oscillator on the FPGA board has a period of 10 nanoseconds. By implementing a counter that increments from 0 to 9 and then repeats, a new sequence is generated with a period of 100 nanoseconds (10 counts × 10 ns per count). This process effectively divides the input clock frequency by a factor of 10, resulting in a lower output frequency.
When comparing these two designs, it is crucial to understand the relationship between the RTL (Register Transfer Level) code and the synthesized results. Specifically, pay attention to the timing of condition evaluations and when the designated operations are executed.
Is it feasible to dynamically modify the counter's upper bound limit, while minimizing the amount of code changes required to implement this functionality? Consider the following design. It generates two count sequences simultaneously. One sequence increments from 0 to 239, while the other sequence counts from 0 to 999. Both sequences are produced concurrently within the same module.
RTL Reference (count-240 & count-1000)
RTL Reference (count-240 & count-1000)
You can simulate the circuit using the default parameter values specified within the RTL code.
Testbench Reference (count-240 & count-1000)
Testbench Reference (count-240 & count-1000)
Simulation results (count-240 & count-1000)
Simulation results (count-240 & count-1000)
By employing the parameter overriding technique, you can assign a specific set of parameter values to be used during the simulation process.
Testbench Reference (parameter override)
Testbench Reference (parameter override)
Simulation results (After parameter override)
Simulation results (After parameter override)
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