To implement a 2-bit full adder efficiently, it is advantageous to apply the dataflow modeling approach. By utilizing the "assign" statement in Verilog along with arithmetic operators, you can concisely describe the combinational logic required to perform the addition operation. This method can be easily scaled to construct adders of wider bit widths by extending the vector assignments and operations to accommodate the desired number of bits.
AD2 configuration file download link
https://drive.google.com/file/d/1Niyfz6OFaxRQCPyORPGRQ1do-JyAJix2/view?usp=sharing