Switching Noise Analysis

Goal

The main purpose of this Lab is to find out the switching noise difference between the good and the bad layout. The bad layout is done intentionally bad to exhibit higher switching noise and the good layout is designed with two design principles to reduce switching noise.

1. Usage of continuous return path under the signal traces.

2. Use a low inductance decoupling capacitor close to the IC power pin.

Plan of Record

Features of the Board

1. Low Drop Out (LDO) is used to generate 3.3V stable voltage supply from 5V supply.

2. It has a fast 555 timer IC.

3. Designed to generate a square wave of approximately 500 Hz and a duty cycle of 66%.

4. Two hex inverters are used in this board, each at good and bad layout side.

5. Used red LEDs and 47Ω resistors as the load to three of the switching outputs of each hex inverter.

6. The output of the fourth switching inverter is connected to a test point to act as a trigger for the scope.

7. One output of each hex inverter is set as a quiet HIGH and one output as a quiet LOW.

8. The layout is engineered in such a way that on one side the board is designed with best design practices and on the other side of the board with bad layout practices. In the bad layout, the decoupling capacitor is placed far away from the Vcc pin.

9. The decoupling capacitor is placed near the input of the 555 timer IC to reduce switching noise in a good layout side.

10. The Bottom layer of the PCB is poured with copper and used as a ground plane in good layout side.

Schematic

Layout

Switching Noise seen at Quite low victim line of a Good Layout design

Switching Noise seen at Quite low victim line of a Bad Layout design