Back-End-Of-Line

3-1. Ultra Low-k Dielectric for Back-End-Of-Line

Introducing a novel approach to depositing a dielectric film that addresses the limitations in process, electrical, and mechanical aspects of existing PECVD-based ultra-low-k (ULK) materials. This advancement enables seamless integration with metal wiring structures in the current semiconductor industry. Through the utilization of iCVD, a ULK polymer dielectric film with a dielectric constant (k) of 2.2 is synthesized at room temperature, providing electrical performance on par with SiCOH, an inorganic material. Comprehensive evaluations of electrical reliability are conducted, and a library is being planned. The research focuses on an integration pathway that prevents metal precursors from infiltrating the wiring process. Furthermore, precise evaluation of the RC delay will be carried out by integrating the film into the device spacer. (Co-work with KIST)

3-2. Barrier-less for blocking of precursor and fluorine penetration

Low dielectric constant polymer material minimizes material penetration during the subsequent wiring process and prevents leakage current between layers. Through the iCVD process, monomers with various fluorocarbon chain lengths are used to secure fluorine-based low dielectric constant polymer materials that do not require a barrier. Developed a dielectric film with low dielectric constant and surface energy by introducing a laminate of an organosiloxane-based low-dielectric constant polymer and a fluorine-based polymer with very low surface energy.

3-3. Patterning & Reliability of ULK

Securing process conditions that allow insulating films to be deposited on the surface of various substrates made of two or more types of insulating films/metals. Evaluation of dry etching conditions with a uniform surface and anisotropic properties is essential. In particular, research was conducted by setting a target value to increase reliability by minimizing the roughness of the etched area corresponding to the side wall. We are securing and optimizing a plating process that can fill the wiring area formed by the etching process with Cu. Since fill defects can reduce the reliability of wiring, we conducted research by setting target values for specific resistance and cross-section void size.