Vídeos educativos

Vídeos educativos alojados no YouTube

(O número de visualizações apresentado para cada vídeo diz respeito à data de 01.09.2022.)

(Ordem) Visualizações - Duração - Data de criação - Título com apontador para o YouTube

(148) 22 - 02:43 - 19.01.2022 - DFDS3200 2021/22 BST: Short circuits in different chains

(147) 14 - 04:53 - 19.01.2022 - DFDS3200 2021/22 BST: Detection of shorts and opens

(146) 28 - 03:23 - 19.01.2022 - DFDS3200 2021/22 BST: Short faults in TAP pins

(145) 87 - 04:10 - 19.01.2022 - DFDS3200 2021/22 BST: Test protocol and procedures

(144) 54 - 03:40 - 13.12.2021 - DFDS3200 2021/22: Welcome

(143) 43 - 01.13 - 09.12.2021 - A sala de aulas é em todo o lado (3/3: Pegada digital)

(142) 48 - 01:46 - 09.12.2021 - A sala de aulas é em todo o lado (2/3): Preparação da UC

(141) 70 - 03:25 - 09.12.2021 - A sala de aulas é em todo o lado (1/3): Apresentação geral

(140) 18 - 04:51 - 29.10.2021 - CS4110 2021/22: Codesign (3/3) Concurrency and parallelism

(139) 22 - 10:54 - 29.10.2021 - CS4110 2021/22: Codesign (2/3) Codesign space

(138) 56 - 05:03 - 29.10.2021 - CS4110 2021/22: Codesign (1/3) Appl. domain, dist. features

(137) 34 - 03:51 - 29.10.2021 - CS4110 2021/22: Assessment

(136) 101 - 06:01 - 29.10.2021 - CS4110 2021/22: Welcome

(135) 72 - 04:32 - 14.03.2021 - Seminário U.Porto: Educação em modo dual

(134) 35 - 04:09 - 27.11.2020 - DFDS3200 2020/21: Welcome

(133) 68 - 07:38 - 23.06.2020 - CS4110 2020/21: Welcome

(132) 25 - 04:25 - 23.06.2020 - CS4110 2020/21: Assessment

(131) 69 - 03:00 - 15.04.2020 - Seminário UPT: Introdução

(130) 45 - 02:44 - 02.02.2020 - Array sorting coursework assignment

(129) 254 - 04:06 - 02.02.2020 - Napoleon’s cipher coursework assignment

(128) 112 - 08:06 - 31.12.2019 - The TAP controller

(127) 109 - 06:40 - 31.12.2019 - The BS instructions

(126) 97 - 05:19 - 31.12.2019 - The on-chip BS architecture

(125) 127 - 05:27 - 31.12.2019 - The basic BS cell

(124) 179 - 05:35 - 31.12.2019 - DFDS3200 2019/20 BST (1/5): Why, What for, How?

(123) 27 - 03:52 - 31.12.2019 - ES-SHC4300 2019/20 00-Welcome

(122) 43 - 03:50 - 31.12.2019 - DFDS3200 2019/20 00-Welcome

(121) 90 - 01:14 - 15.07.2019 - VHDL101 01c 2:4 decoder demo (2:4 decoder demo)

(120) 66 - 07:59 - 11.07.2019 - VHDL101 08c SimpleCPU (design hints 2)

(119) 106 - 05:26 - 11.07.2019 - VHDL101 08b SimpleCPU (design hints 1)

(118) 82 - 06:22 - 11.07.2019 - VHDL101 08a SimpleCPU (project description)

(117) 39 - 05:53 - 11.07.2019 - VHDL101 07b MusicBox (design hints)

(116) 43 - 07:24 - 11.07.2019 - VHDL101 07a MusicBox (project description)

(115) 67 - 04:39 - 11.07.2019 - VHDL101 06c FSMD (FSMD-based e-dice)

(114) 359 - 06:17 - 11.07.2019 - VHDL101 06b FSMD (FSMD representations)

(113) 234 - 05:19 - 11.07.2019 - VHDL101 06a FSMD (ABC of FSMD)

(112) 64 - 04:48 - 11.07.2019 - VHDL101 05c FSM (FSM-based e-dice)

(111) 107 - 07:05 - 11.07.2019 - VHDL101 05b FSM (FSM representations)

(110) 233 - 08:11 - 11.07.2019 - VHDL101 05a FSM (ABC of FSM)

(109) 199 - 06:28 - 11.07.2019 - VHDL101 04c RegSeqCircuits (counter e-dice)

(108) 105 - 05:01 - 11.07.2019 - VHDL101 04b RegSeqCircuits (RSC design verification)

(107) 241 - 07:58 - 11.07.2019 - VHDL101 04a RegSeqCircuits (ABC of sequential circuits)

(106) 98 - 06:11 - 09.07.2019 - VHDL101 03b CombCircuits (CC: design verification)

(105) 260 - 07:30 - 09.07.2019 - VHDL101 03a CombCircuits (ABC of combinational circuits)

(104) 139 - 08:35 - 09.07.2019 - VHDL101 02e Groundwork (FPGA fabric)

(103) 157 - 07:55 - 09.07.2019 - VHDL101 02d Groundwork (main conc. and seq. statements)

(102) 127 - 06:37 - 09.07.2019 - VHDL101 02c Groundwork (operators, data types, statements)

(101) 156 - 07:43 - 09.07.2019 - VHDL101 02b Groundwork (VHDL descriptions)

(100) 372 - 08:41 - 09.07.2019 - VHDL101 02a Groundwork (ABC of VHDL)

(099) 371 - 08:45 - 09.07.2019 - VHDL101 01b LabSetup (Vivado and Basys-3 demo)

(098) 233 - 03:30 - 09.07.2019 - VHDL101 01a LabSetup (Vivado and Basys-3 files installation)

(097) 84 - 03:26 - 09.07.2019 - VHDL101 00 Welcome

(096) 36 - 03:41 - 09.07.2019 - OOP4200 19/20 00 Welcome

(095) 58 - 03:41 - 09.07.2019 - DFDV3100 19/20 00 Welcome

(094) 19 - 03:40 - 13.12.2018 - DFDS3200 Digital Systems 18/19 Acquaintance and welcome

(093) 59 - 04:02 - 10.12.2018 - DFDV3100 Course syllabus presentation

(092) 99 - 06:02 - 10.12.2018 - DFDV3100 Memory hierarchy design (cache systems)

(091) 16 - 03:10 - 10.12.2018 - DFDV3100 Work plan and teaching and learning model

(090) 124 - 07:40 - 10.12.2018 - DFDV3100 ILP + its exploitation | Instruction pipelining

(089) 231 - 07:21 - 10.12.2018 - DFDV3100 Fundam. of quantitative design and analysis 02

(088) 96 - 07:50 - 10.12.2018 - DFDV3100 ILP + its exploitation: Parallelism beyond pipelining

(087) 79 - 04:54 - 10.12.2018 - DFDV3100 DLP | GPU architectures

(086) 1 178 - 04:29 - 10.12.2018 - DFDV3100 DLP | Vector and SIMD architectures

(085) 470 - 06:09 - 10.12.2018 - DFDV3100 TLP | Models and challenges

(084) 119 - 08:36 - 10.12.2018 - DFDV3100 Memory hierarchy design (direct-mapped caches)

(083) 20 - 05:20 - 10.12.2018 - DFDV3100 w13a CCW assignment | Logo CPU

(082) 691 - 07:46 - 10.12.2018 - DFFDV3100 Fundam. of quantitative design and analysis 01

(081) 72 - 16:36 - 21.01.2018 - Vivado 2017.3 Demo

(080) 64 - 03:47 - 28.12.2017 - DFDS3200 1-st Part-1a Welcome

(079) 43 - 07:34 - 26.07.2016 - DFDS3101 pedagogy assessment and resources

(078) 124 - 05:07 - 26.07.2016 - Installation of Vivado and Basys-3 board files

(077) 124 - 12:38 - 23.10.2016 - CCW3: BS controller spec

(076) 87 - 06:10 - 12.10.2016 - CCW2: music box spec

(075) 123 - 01:16 - 06.10.2016 - CCW2: music box demo

(074) 62 - 02:07 - 06.10.2016 - UART test

(073) 111 - 08:08 - 13.09.2016 - CCW1: cheating e-dice spec

(072) 64 - 01:59 - 04.09.2016 - CCW1: cheating e-dice demo

(071) 73 - 09:07 - 25.10.2015 - 10- CCW3 Spec: BST architecture

(070) 9 - 01:07 - 17.10.2015 - W09_Q22_e-piano_demo

(069) 37 - 03:58 - 12.10.2015 - 08b- CCW2 e-lock demo

(068) 26 - 02:44 - 11.10.2015 - 7e- W08_Q18_UART

(067) 35 - 08:43 - 04.10.2015 - 8a- CCW2 e-lock spec

(066) 73 - 03:39 - 27.09.2015 - 7d- Interface Circuit (UART)

(065) 86 - 09:22 - 27.09.2015 - 7c- ASMD chart and VHDL description (UART)

(064) 85 - 07:59 - 27.09.2015 - 7b- Receiver Operation (UART)

(063) 130 - 07:48 - 27.09.2015 - 7a- Basic Concepts (UART)

(062) 53 - 08:26 - 20.09.2015 - 6c- Debouncer VHDL

(061) 65 - 08:33 - 20.09.2015 - 6b- Debouncer ASMD

(060) 129 - 09:18 - 20.09.2015 - 6a- Basic Concepts

(059) 22 - 02:27 - 19.09.2015 - 05b CCW1 e-dice demo

(058) 54 - 09:32 - 13.09.2015 - 05a CCW1 e-dice spec

(057) 24 - 01:51 - 05.09.2015 - Listing 4.14 Demo

(056) 63 - 08:49 - 03.09.2015 - 4c- Rising edge detector

(055) 84 - 08:35 - 03.09.2015 - 4b- FSM representations

(054) 133 - 05:14 - 03.09.2015 - 4a- Basic concepts

(053) 154 - 06:43 - 01.09.2015 - 3a- Basic concepts

(052) 81 - 04:50 - 01.09.2015 - 3b- Two-segment coding style

(051) 71 - 07:49 - 01.09.2015 - 3c- 8-bit registers

(050) 63 - 05:23 - 01.09.2015 - 3d- Binary counters

(049) 9 - 05:56 - 01.09.2015 - 4- Binary Counters (discarded)

(048) 6 - 08:58 - 01.09.2015 - 3- 8-bit registers (discarded)

(047) 5 - 05:12 - 01.09.2015 - 2- Two-segment coding style (discarded)

(046) 6 - 06:42 - 01.09.2015 - 1- Basic concepts reg seq circuits (discarded)

(045) 25 - 01:31 - 31.08.2016 - Hangout Week 02 demo

(044) 40 - 07:32 - 06.08.2015 - 1a- Pedagogy assessment resources for DFDS 3101

(043) 60 - 05:36 - 06.08.2015 - 1b- Xilinx ISE 14 7 installation

(042) 176 - 06:06 - 06.08.2015 - 2a- What is in a VHDL description

(041) 109 - 05:05 - 06.08.2015 - 2b- Operators and data types

(040) 83 - 05:12 - 06.08.2015 - 2c- Concurrent statements

(039) 64 - 04:42 - 06.08.2015 - 2d- Sequential statements

(038) 2 368 - 09:25 - 02.08.2015 - 09a- Why, What for, How?

(037) 1 593 - 07:10 - 02.08.2015 - 09b- The basic BS cell

(036) 1 200 - 06:36 - 02.08.2015 - 09c- The on-chip BS architecture

(035) 2 187 - 07:38 - 02.08.2015 - 09d- The BS instructions

(034) 19 580 - 08:37 - 02.08.2015 - 09e- The TAP controller

(033) 76 - 14:17 - 26.10.2014 - Final CW CP operation (OperMicro CParch DFDS3101 14/15)

(032) 133 - 17:55 - 26.10.2014 - Final CW Presentation (uprogrammed BS test coprocessor)

(031) 253 - 09:05 - 05.10.2014 - ABC Player Spec for 2014/15

(030) 86 - 13:46 - 07.11.2013 - SESH Final Coursework Hints 1 (BS ctr: Int Hex dec function)

(029) 70 - 14:09 - 07.11.2013 - DFDSFinal Coursework Hints 1 (BS ctr: Int Hex dec function)

(028) 84 - 11:38 - 31.10.2013 - SESH Final Coursework (BS ctrl: Emb core, micropro, FSMD)

(027) 77 - 10:02 - 31.10.2013 - DFDS Final Coursework (BS ctrl: PicoBlaze)

(026) 283 - 17:36 - 14.10.2013 - ABC Player Hints 2

(025) 377 - 21:58 - 07.10.2013 - ABC Player Hints 1

(024) 2 724 - 21:11 - 21.09.2013 - VHDL in Practice 1 - FSMD

(023) 12 448 - 26:35 - 21.09.2013 - VHDL in Practice 2 - UART

(022) 275 - 12:52 - 21.09.2013 - Course assignments 1 (ABC player)

(021) 294 - 02:45 - 18.09.2013 - VHDL_Intro_1_Whats_in_a_VHDL_description

(020) 99 - 11:09 - 18.09.2013 - VHDL_Intro_2_Xilinx_ISE

(019) 196 - 16:44 - 18.09.2013 - VHDL_Intro_3_RT-level_combinational_design

(018) 208 - 25:44 - 18.09.2013 - VHDL_Intro_4_Regular_sequential_circuits

(017) 229 - 16:57 - 18.09.2013 - VHDL_Intro_5_Finite_state_machines

(016) 3 620 - 05:34 - 01.08.2013 - BST-1 (The BST technology)

(015) 2 285 - 06:04 - 01.08.2013 - BST-2 (The basic BS cell)

(014) 1 490 - 06:43 - 01.08.2013 - BST-3 (BS: The test architecture)

(013) 1 675 - 08:11 - 01.08.2013 - BST-4 (The BS instructions)

(012) 2 064 - 09:41 - 01.08.2013 - BST-5 (The TAP controller)

(011) 337 - 08:12 - 01.08.2013 - Demo-3 (demo board: non-BS clusters)

(010) 458 - 11:12 - 01.08.2013 - Demo-2 (demo board: led experiment)

(009) 875 - 05:30 - 01.08.2013 - Demo-1 (demo board: fault insertion features)

(008) 294 - 10:44 - 01.08.2013 - PRPG-PSA-1 (PRPG / PSA basics)

(007) 169 - 10:33 - 01.08.2013 - PRPG-PSA-2 (PRPG / PSA testing)

(006) 1 126 - 10:15 - 01.08.2013 - Fault-detection-1 (Test protocol and test procedures)

(005) 472 - 10:19 - 01.08.2013 - Fault-detection-2 (shorts affecting TAP pins)

(004) 433 - 10:56 - 01.08.2013 - Fault-detection-3 (open circuit faults: open X1)

(003) 457 - 09:12 - 01.08.2013 - Fault-detection-4 (shorts in pins of different chains: short X9)

(002) 19 - 01:39 - 05.02.2012 - HIBU2K12: Init seq (clmn addr, page addr, data byte all-1)

(001) 223 - 01:34 - 05.02.2012 - HIBU2K12: Explanation of the ASM diagram