NICS Design Lab - Conference

* Corresponding Authorship

2024

[32] [Domestic] M. Jeon, J. Lee, J. Choi, and J.-H. Chae*, "A 16-kb 8T1C SRAM Computing-in-Memory using 2-Step Charge/Discharge Based on Capacitive Coupling," to be presented in ISE Summer Annual Conference, July 2024.
[31] H. Cheon‡, H. Lee‡, J. Lee, I. Jeon, and J.-H. Chae*, "A 16-Kb 1T1C DRAM supporting conventional and compute-in-memory access modes," to be presented in 21st International SoC Design Conference (ISOCC), Aug. 2024.. (‡: Equally contribution.)
[30] J. Lee, H. Lee, H. Cheon, I. Jeon, and J.-H. Chae*, "Design of 16-Kb 6T SRAM supporting wide parallel data access for enhanced computation speed," to be presented in 21st International SoC Design Conference (ISOCC), Aug. 2024.
[29] One of Major Conferences in IC Design D. Kim, J.-Y. Kim, H. Cho, S. Yoo, S. Lee, S. Yune, H. Jeong, K. Park, K.-S. Lee, J. Lee, C. Han, G. Koo, Y. Han, J. Kim, J. Kim, K. Lee, J.-H. Chae, K. Cho, J.-Y. Kim, "DPIM: A 19.36TOPS/W 2T1C eDRAM transformer-in-memory chip with sparsity-aware quantization and heterogeneous dense-sparse core," to be presented in European Solid-State Electronics Research Conference(ESSERC), Sept. 2024.
[28] Top Conference in IC Design C. Han‡, K.-S. Lee‡, and J.-H. Chae*, "A 25.2-Gb/s/pin NRZ/PAM-3 dual-mode transmitter with embedded partial DBI achieving 133% I/O bandwidth/pin efficiency and 19.3% DBI efficiency," in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024, pp. 248-249. (‡: Equally contribution.)
[27] H. Lee and J.-H. Chae*, "A 1-Kb 6T 1C XNOR-DRAM compute-in-memory macro with signed bit adder block for CNN operations," in 2024 International Conference on Electronics, Information, and Communication (ICEIC), Jan. 2024, pp. 152-155.

2023

[26] Y.-U. Jeong, S. Choi, S. Kim, and J.-H. Chae*, "A single-ended receiver-side crosstalk cancellation with independent gain and timing control for minimum residual FEXT," in 2023 IEEE International Symposium on Integrated Circuits and Systems (ISICAS), Oct. 2023.
[25] [Domestic] C.-H. Han and J.-H. Chae*, "Design of CLK lane transceiver for 3.2Gb/s forwarded clocking system," in IEIE Summer Annual Conference, June 2023, pp. 96-100.
[24] [Domestic] K.-S. Lee and J.-H. Chae*, "Design of single-ended NRZ receiver for memory interfaces using quarter-rate clocking architecture," in IEIE Summer Annual Conference, June 2023, pp. 92-95.
[23] [Domestic] J.-C. Lee and J.-H. Chae*, "ZQ code analysis and effect for impedance matching of single-ended NRZ voltage-mode driver," in IEIE Summer Annual Conference, June 2023, pp. 181-185.
[22] [Domestic] B.-D. Choi and J.-H. Chae*, "Design of a 30-Gb/s PAM-3 transmitter with 2-tap feed-forward equalizer for next-generation memory interfaces," in IEIE Summer Annual Conference, June 2023, pp. 192-196.
[21] B.-D. Choi and J.-H. Chae*, "A 21-Gb/s PAM-3 driver using ZQ calibration with middle-level calibration to improve level separation mismatch ratio," in 38th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June 2023, pp. 160-165.
[20] W.-G. Lee and J.-H. Chae*, "Improvement of data retention time in gain-cell embedded DRAM using MOMCAP," in 38th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June 2023, pp. 155-159.
[19] J.-C. Lee, T.-O. Kim, and J.-H. Chae*, "Module implementation and simulation of timing constraint check function of I2C protocol using Verilog," in 2023 International Conference on Electronics, Information, and Communication (ICEIC), Feb. 2023.

2022

[18] [Domestic] J.-W. Lee and J.-H. Chae*, "Data retention time phenomenon of various 2T gain cell embedded DRAMs according to PVT variation," in 2022 IEIE Autumn Annual Conference, Nov. 2022, pp. 493-496.
[17] [Domestic] H.-J. Cheon and J.-H. Chae*, "3T GC-eDRAM analysis for low power VLSI SoC optimization," in IEIE Autumn Annual Conference, Nov. 2022, pp. 119-124.
[16] [Domestic] S.-I. Kang‡, D.-W. Kang‡, and J.-H. Chae*, “32Gb/s PAM-4 transmitter design and 1-tap FFE effectiveness analysis,” in IEIE Autumn Annual Conference, Nov. 2022, pp. 511-515. (‡: Equally contribution)
[15] [Domestic] J.-S. Shin, B.-D. Choi, and J.-H. Chae*, “Design of digital-based 24-bit parallel PRBS generator for PAM-3 signaling,” in ISE Summer Annual Conference, July 2022, pp. 32-33.
[14] [Domestic] B.-D. Choi and J.-H. Chae*, “Design of ZQ calibration circuit for single-ended voltage-mode PAM-3 driver,” in IEIE Summer Annual Conference, June 2022, pp. 66-69.
[13] [Domestic] D.-W. Kang‡, S.-I. Kang‡, and J.-H. Chae*, “Modeling of PRBS generator and serializer using Verilog-A and comparative analysis of conventional and LVSTL driver,” in IEIE Summer Annual Conference, June 2022, pp. 230-233. (‡: Equally contribution)
[12] [Domestic] K.-S. Lee‡, J.-W. Song‡, W.-K. Hong‡, and J.-H. Chae*, “Design and evaluation of a reliable physical unclonable function insensitive to temperature and supply voltage variation,” in IEIE Summer Annual Conference, June 2022, pp. 244-247. (‡: Equally contribution)

2021

[11] H. Park, J. Park, J.-W. Lee, Y.-U. Jeong, S. H. Jeong, S. Kim, and J.-H. Chae*, “A high-accuracy and fast-correction quadrature signal corrector using an adaptive delay gain controller for memory interfaces,” in IEEE International Symposium on Circuits and Systems (ISCAS), May 2021.
[10] Top Conference in IC Design K. Kim, J.-H. Chae, J. Yang, J. Kang, et. al., “A 24Gb/s/pin 8Gb GDDR6 with half-rate daisy-chain-based clocking architecture with I/O circuitry for low-noise operation,” in IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2021, pp. 344-346.

2020

[9] Y.-U. Jeong, J. Park, M. Kim, J.-H. Chae, J. Yun, H. Lee, and S. Kim, “A 9Gb/s wide output range transmitter with 2D binary-segmented driver and dual-loop calibration for intra-panel interfaces,” in IEEE International Symposium on Integrated Circuits and Systems (ISICAS), Aug. 2020.

2019

[8] Y.-U. Jeong, J.-H. Chae, S. Choi, J. Yun, S.-H. Jeong, and S. Kim, "A low-power low-noise 20:1 serializer with two calibration loops in 55-nm CMOS," in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2019.
[7] C. Hyun, H. Ko, J.-H Chae, H. Park, and S. Kim, “A 20Gb/s dual-mode PAM-4/NRZ single-ended transmitter with RLM compensation," in IEEE International Symposium on Circuits and Systems (ISCAS), May 2019.

2018

[6] J.-W. Lee, J.-H. Chae, J. Park, H. Park, J. Yun, and S. Kim, “Energy-efficient dynamic comparator with active inductor for receiver of memory interfaces," in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Jul. 2018, pp. 10-15.

2017

[5] One of Major Conferences in IC Design J. Park, J.-H. Chae, Y.-U. Jeong, J.-W. Lee, and S. Kim, “A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface," in IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2017, pp. 257-260.
[4] M. Kim, J. Park, J.-H. Chae, H. Ko, M. Kim, and S. Kim, “An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface,” in 14th International SoC Design Conference, Nov. 2017, pp. 286-287.
[3] J. Park, G.-M. Hong, M. Kim, J.-H. Chae, and S. Kim, “A 0.13pJ/bit referenceless transceiver with clock edge modulation for a wired intra-BAN communication,” in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Jul. 2017, pp. 1-6.

2015

[2] One of Major Conferences in IC Design J.-H. Chae, G.-M. Hong, J. Park, M. Kim, H. Ko, W.-Y. Shin, H. Chi, D.-K. Jeong, and S. Kim, “A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers,” in IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2015, pp. 109-112.

2013

[1] One of Major Conferences in IC Design M. Kim, W.-Y. Shin, G.-M. Hong, J. Park, J.-H. Chae, N. Xing, J.-K. Woo, and S. Kim, “High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line,” in IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2013, pp. 311-314.