Research Interest: Memory/Sense Amplifier Design, In-Memory Computing

Dissertation Title: A Capacitor-Coupled Offset-Cancelling and Charge Transfer Pre-Sensing Bit-Line Sense Amplifier for DRAMs

Research Interest: High-Speed Memory/Wireline/Die-to-Die Interface

Dissertation Title: A Run-Length-Tolerant Transition-Driven AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces

Research Interest: High-Speed Memory Interface

Dissertation Title: PAM-3 Single-Ended Voltage-Mode Transmitter with ZQ calibration for Impedance Matching

Current Affiliation: LeoLSI

Research Interest: High-Speed Memory/Wireline Interface

Dissertation Title: A Stack-Reduced-Slicer-Based Single-Ended Receiver with Embedded 1-Tap Decision Feedback Equalizer for Next-Generation Low-Power Memory Interfaces

Research Interest: Memory Design, In-Memory Computing

Dissertation Title: Design of a 6T SRAM Macro with Enhanced Read Speed in Wide Parallel Data Access Mode and Assist Circuit for Stable Operation

Current Affiliation: Micron

Research Interest: High-Speed Memory/Wireline Interface 

Dissertation Title: High-Speed Serializer Timing Error Detection Circuit and Single-Ended Transmitter with Main and Sub Pre-Emphasis FFE for Low-Power Memory Interfaces

Current Affiliation: LeoLSI

Research Interest: Memory Design, In-Memory Computing

Dissertation Title: Design of 16-Kb 1T1C DRAM Achieving Enhanced Read Speed Through Compute-in-Memory Access Mode

Current Affiliation: Global Technology

Research Interest: High-Speed Memory/Wireline Interface

Dissertation Title: NRZ/PAM-3/PAM-4 Tri-Mode Transmitter for Memory Interface