Research Interest: High-Speed Memory/Wireline Interface 

E-Mail: bonajiwon (at) kw.ac.kr

Dissertation Title: Design of a 6T SRAM Macro with Enhanced Read Speed in Wide Parallel Data Access Mode and Assist Circuit for Stable Operation

Current Affiliation: Micron

Research Interest: High-Speed Memory/Wireline Interface 

E-Mail: dlwhdcks0129 (at) kw.ac.kr

Dissertation Title: High-Speed Serializer Timing Error Detection Circuit and Single-Ended Transmitter with Main and Sub Pre-Emphasis FFE for Low-Power Memory Interfaces

Current Affiliation: Kwangwoon University

Research Interest: Memory Design, In-Memory Computing

E-Mail: guswnsl113 (at) kw.ac.kr

Dissertation Title: Design of 16-Kb 1T1C DRAM Achieving Enhanced Read Speed Through Compute-in-Memory Access Mode

Current Affiliation: CoresSol

Research Interest: High-Speed Memory/Wireline Interface

E-Mail: jiangjiao (at) kw.ac.kr

Dissertation Title: NRZ/PAM-3/PAM-4 Tri-Mode Transmitter for Memory Interface