NICS Design Lab

* Corresponding Authorship

H.-S. Lee, I.-H. Jeon, J. Lee, and J.-H. Chae*, "TBD," TBD.
Y.-U. Jeong and J.-H. Chae*, "TBD," TBD.
J. Lee and J.-H. Chae*, "TBD," TBD.
J.-C. Lee, C. Han, and J.-H. Chae*, "TBD," TBD.

C. Han‡, K.-S. Lee‡, J.-C. Lee, and J.-H. Chae*, "XXX," XXX. (‡: Equally contribution.)
H.-S. Lee, I.-H. Jeon, J. Lee, E. Ko, and J.-H. Chae*, "XXX," XXX.
J. Lee and J.-H. Chae*, "XXX," XXX.
H.-S. Lee‡, I.-H. Jeon‡, J. Lee, H. Cheon, and J.-H. Chae*, "XXX," XXX. (‡: Equally contribution.)
I.-H. Jeon and J.-H. Chae*, "XXX," XXX.

2024

[33] Q1, IF: 4.6 C. Han‡, K.-S. Lee‡, and J.-H. Chae*, "25.2-Gb/s/pin NRZ/PAM-3 dual-mode transmitter with embedded partial DBI: improving I/O bandwidth/pin and DBI efficiencies," to be published in the IEEE Journal of Solid-State Circuits (JSSC). (‡: Equally contribution.)
[32] J.-H. Chae*, "High-bandwidth and energy-efficient memory interfaces for the data-centric era: recent advances, design challenges, and future prospects," to be published in the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS).
[31] Q1, IF: 5.2 Y.-U. Jeong and J.-H. Chae*, "A single-ended PAM-4 transmitter using unstacked tailless CML driver and coefficient-corrected FFE for memory interfaces," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 71, no. 12, pp. 6306-6315, Dec. 2024.
[30] Q2, IF: 3.4 J. Lee and J.-H. Chae*, "Debugging circuit for detecting timing errors in serializer for high-speed wireline interfaces," IEEE Access, vol. 12, pp. 164352-164358, Nov. 2024.
[29] Q1, IF: 5.6 Y.-U. Jeong and J.-H. Chae*, "Per-DFE offset measurement and cancellation of weighted-VREF-based loop-unrolled DFE for memory interfaces," IEEE Transactions on Instrumentation and Measurement (TIM), vol. 73, pp. 1-8, Oct. 2024.
[28] [Domestic] 한국연구재단 등재지 J. Jiao and J.-H. Chae*, "Design of NRZ/PAM-3/PAM-4 tri-mode single-ended transmitter for next-generation memory interfaces," Journal of Integrated Circuits and Systems (JICAS), vol. 10, no. 4, pp. 1-7, Oct. 2024.
[27] Q1, IF: 4.6 J. Yun, S. Lee, J. Kim, J.-H. Chae, S. Kim, and Y.-U. Jeong, "A single-ended impedance-matched transmitter with single ring-oscillator based time-domain ZQ calibration for memory interfaces," IEEE Journal of Solid-State Circuits (JSSC), vol. 59, no. 9, pp. 2971-2982, Sept. 2024.
[26] [Domestic] 한국연구재단 등재지 J.-C. Lee and J.-H. Chae*, "Design of 2.5-Gb/s parallel PRBS generator and 4-Gb/s area efficient PRBS checker in 65-nm CMOS process," Journal of Integrated Circuits and Systems (JICAS), vol. 10, no. 1, Jan. 2024.

2023

[25] Q1, IF: 5.6 J.-H. Chae*, "Design of clocked comparator preventing bit errors to improve reliability of low-speed DRAM measurement," IEEE Transactions on Instrumentation and Measurement (TIM), vol. 72, pp. 1-10, 2023.
[24] Q1, IF: 5.1 (ISICAS'23 Special Issue) Y.-U. Jeong, S. Choi, S. Kim, and J.-H. Chae*, "A single-ended receiver-side crosstalk cancellation with independent gain and timing control for minimum residual FEXT," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 70, no. 12, pp. 4793-4803, Dec. 2023.
[23] Q1, IF: 5.4 Y.-U. Jeong, J.-H. Chae, and S. Kim, "A 0.85-pJ/b 16-Gb/s/pin single-ended transmitter with integrated voltage modulation for low-power memory interfaces," IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 9, pp. 2659-2667, Sept. 2023.
[22] Q2, IF: 3.9 J. Kim, J. Yun, J.-H. Chae, and S. Kim, "A 50-1600MHz wide-range digital duty-cycle corrector with counter-based half-cycle delay line," IEEE Access , vol. 11, pp. 30555-30561, Mar. 2023.

2022

[21] Q2, IF: 3.691 S. Lee, Y.-U. Jeong, J. Yun, J.-H. Chae, and S. Kim, "A low-power DRAM transmitter with phase and current-mode amplitude equalization to improve impedance matching," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 69, no. 11, pp. 4208-4212, Nov. 2022.
[20] Q2, IF: 3.476 J.-H. Chae*, Y.-U. Jeong, and B.-D. Choi, "Design and comparative study of voltage regulation-based 2-tap flexible feed-forward equalizer for voltage-mode transmitter," IEEE Access , vol. 10, pp. 37446-37456, Apr. 2022.
[19] Q2, IF: 4.140 Y.-U. Jeong, S. Choi, J.-H. Chae, J. Yun, S.-H. Jeong, and S. Kim, "A 10 Gb/s/pin single-ended transmitter with reflection-aided duobinary modulation for dual-rank mobile memory interfaces," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 69, no. 3, pp. 1125-1134, Mar. 2022.
[18] Q1, IF: 6.126 (ISSCC'21 Special Issue) J. Kang, J. Yang, K. Kim, J.-H. Chae et. al., “A 24Gb/s/pin 8Gb GDDR6 with half-rate daisy-chain-based clocking architecture with I/O circuitry for low-noise operation,” IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 1, pp. 212-223, Jan. 2022.

2021

[17] Q2, IF: 3.367 S. Choi, Y.-U. Jeong, J.-H. Chae, S.-H. Jeong, and S. Kim “A differentiating receiver with a transition-detecting DFE for dual-rank mobile memory interface,” IEEE Access, vol. 9, pp. 120285-120296, Sept. 2021.
[16] Q1, IF: 5.013 H. Ko, M. Kim, H, Park, S, Lee, J. Kim, S. Kim, and J.-H. Chae*, “A controller PHY for managed DRAM solution with damping-resistor-aided pulse-based feed-forward equalizer,” IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 8, pp. 2563-2573, Aug. 2021.
[15] Q3, IF: 2.397 C. Hyun, Y.-U. Jeong, S. Kim, and J.-H. Chae*, "An 18-Gb/s/pin single-ended PAM-4 transmitter for memory interfaces with adaptive impedance matching and output level compensation," Electronics, vol. 10, no. 15, pp.1768, July 2021.
[14] Q1, IF: 5.013 (SOVC'20 Special Issue) Y.-U. Jeong, H. Park, C. Hyun, J.-H. Chae, S.-H. Jeong, and S. Kim, “A 0.64-pJ/bit 28-Gb/s/pin high-linearity single-ended PAM-4 transmitter with an impedance-matched driver and three-point ZQ calibration for memory interface,” IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 4, pp. 1278-1287, Apr. 2021.

2020

[13] Q2, IF: 2.814 S. Lee, H.-G. Ko, J.-H. Chae, S. Shin, J. Yun, D.-K. Jeong, and S. Kim, "A 0.83-pJ/bit 6.4-Gb/s HBM Base Die Receiver using a 45° Strobe Phase for Energy-Efficient Skew Compensation," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 67, no. 10, pp.1735-1739, Oct. 2020.
[12] Q2, IF: 3.318 J.-H. Chae, Y.-U. Jeong, and S. Kim, “Data-dependent selection of amplitude and phase equalization in a quarter-rate transmitter for memory interfaces,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 67, no. 9, pp.2972-2983, Sept. 2020.
[11] Q2, IF: 2.814 (ISICAS'20 Special Issue) Y.-U. Jeong, J. Park, M. Kim, J.-H. Chae, J. Yun, H. Lee, and S. Kim, “A 9Gb/s wide output range transmitter with 2D binary-segmented driver and dual-loop calibration for intra-panel interfaces,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 67, no. 9, pp.1589-1593, Sept. 2020.
[10] H. Ko, C. Hyun, J.-H Chae, G.-M. Hong, and S. Kim, “A 3.2GHz quadrature error corrector for DRAM transmitters, using replica serializer and pulse-shrinking delay line,” IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp.38-41, Mar. 2020.
[9] Q2, IF: 2.814 J.-H. Chae, M. Kim, S. Choi, and S. Kim, “A 10.4-Gb/s 1-tap decision feedback equalizer with different pull-up and pull-down tap weights for asymmetric memory interface,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 67, no. 2, pp.220-224, Feb. 2020.

2019

[8] Q2, IF: 1.946 J.-H. Chae, H. Ko, J. Park, and S. Kim, “A quadrature clock corrector for DRAM interfaces, with a duty-cycle and quadrature phase detector based on a relaxation oscillator," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 27, no. 4, pp.978-982, Apr. 2019.
[7] Q2, IF: 3.25 J.-H. Chae, H. Ko, J. Park, and S. Kim, “A 12.8Gb/s quarter-rate transmitter using a 4:1 overlapped multiplexing driver combined with an adaptive clock phase aligner," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 66, no. 3, pp.372-376, Mar. 2019.

2018

[6] Q1, IF: 3.557 J.-H. Chae, M. Kim, G.-M. Hong, J. Park, and S. Kim, “A 3.2Gb/s 16-channel transmitter for intra-panel interfaces, with independently controllable output swing, common-mode voltage, and equalization,” IEEE Access, vol. 6, no. 1, pp. 78055-78064, Dec. 2018.
[5] Q2, IF: 2.45 M. Kim, J.-H. Chae, S. Choi, G.-M. Hong, H. Ko, D.-K. Jeong, and S. Kim, “A 4266Mb/s/pin LPDDR4 interface with an asynchronous feedback CTLE and an adaptive 3-step eye detection algorithm for memory controller,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 65, no. 12, pp. 1894-1898, Dec. 2018.
[4] Q1, IF: 4.075 (ASSCC'17 Special Issue) J. Park, J.-H. Chae, Y.-U. Jeong, J.-W. Lee, and S. Kim, “A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for 55-inch UHD intra-panel interfaces,” IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 10, pp. 2878-2888, Oct. 2018.
[3] Q3, IF: 1.232 H. Ko, J.-H. Chae, and S. Kim, “Single-ended voltage-mode duobinary transmitter with feedback time reduced parallel precoder,” Electronics Letters, vol. 54, no. 26, pp. 936-937, Jul. 2018.

2017

[2] Q3, IF: 1.155 J.-H. Chae, M. Kim, H. Ko, J. Park, G.-M. Hong, D.-K. Jeong, and S. Kim, “A 266-2133MHz phase shifter using all-digital DLL and triangular-modulated phase interpolator for LPDDR4X interface,” Electronics Letters, vol. 53, no. 12, pp. 766-768, Jun. 2017.
[1] Q4, IF: 0.515 J.-H. Chae, M. Kim, G.-M. Hong, J. Park, H. Ko, W.-Y. Shin, H. Chi, D.-K. Jeong, and S. Kim, “0.11-2.5GHz all-digital DLL for mobile memory interface with phase sampling window adaptation to reduce jitter accumulation,” Journal of semiconductor technology and science (JSTS), vol. 17, no. 3, pp. 411-424, Jun. 2017.