In Ki Kim

TCAD process and device simulation of β-Ga₂O₃ vertical MOSFET with a planar gate

Recently, β-Ga₂O₃ has emerged as a new candidate material for high-performance power electronics devices with its wide bandgap (4.84 eV), high breakdown field (8 MV/cm), and high thermal stability. Extensive studies about realization of MOSFET devices based on β-Ga₂O₃ have been reported and various device structures have been proposed. The vertical MOSFET with a planar gate is considered as promising device structure owing to its higher capability on integration density and reliability. In SDSL, the process condition optimization of β-Ga₂O₃ vertical MOSFET with a planar gate for robust device design has been conducted via in-house TCAD process and device simulator.

Three-dimensional process and device simulation of vertically stacked CFET

Three-dimensional simulation of a vertically stacked CFET inverter with 5 nm channel width have been conducted by our in-house simulation. A relevant process flow has been employed and the electrical characteristics of the device are investigated by integrating the generated device structure into the TCAD simulation framework.