Duong Computing - About me

Ủng hộ tôi

Aloha!

I'm Tran Dai Duong (Trần Đại Dương). I am an instructor at University of Information Technology (UIT), Vietnam National University - Ho Chi Minh City, Vietnam.

I received Bachelor of Engineering Degree in Computer Engineering as The Best Graduation Student of FCE in 2016. I have 2 years of experience working at Renesas Design Vietnam as a Hardware Design Engineer since 2015. Since 2018 I have returned to UIT as an instructor. Currently, I am a combined Master's and Ph.D. student under the support of Professor Jae Young Hur at Jeju National University (JNU), South Korea.

I have a Youtube channel, tutorial students on subjects like Operating Systems, Computer Architecture, Digital Logic Design, ...

Objective:

Become an expert in Digital IC Design and Computer Architecture

Research Orientation:

Computer Architecture
Digital Logic Design

Knowledge:

Digital Logic Design: Combination Logic, Sequence Logic, RTL, Verilog HDL, ...
Digital Circuit Design: CMOS, Standard cells, SRAM, ...
Computer Architecture: RISC ISA, MMU, Assembler, micro-Architecture, ...
Computer System Design: Processor, DMA, BUS, ...
Operating System: Memory management, Process/Thread management, I/O management, Virtualization, ...
Programming: OOP, scripting, ...
Data structure: Primitive data type, array, queue, stack, linked list, array list, hash table, bitmap, ...

Hobbies:

Knowledge sharing: blog, tutorials
Manga: Naruto, Onepiece
Game: DotA
Cartoon movie

Publication

Journal

T. D. Duong, Y. S. Kim, and J. Y. Hur, "TLB Coalescing with Range Compressed Page Table for Embedded I/O Devices," in IEEE Access, vol. 13, pp. 12623-12633, 2025, DOI: 10.1109/ACCESS.2025.3528945.
T. D. Duong and J. Y. Hur, "Contiguity Aware TLB Prefetching for Embedded I/O Devices," in IEICE Electronics Express, vol. 22, pp. 20240664, 2025, DOI: 10.1587/elex.21.20240664.
T. D. Duong and J. Y. Hur, "Page-Size Aware Buddy Allocator With Unaligned Range Supports for TLB Coalescing," in IEEE Access, vol. 11, pp. 91850-91860, 2023, DOI: 10.1109/ACCESS.2023.3308591.

Conference

Tran Dai Duong and Jae Young Hur, " Memory Allocation Aware TLB Prefetching for Embedded I/O Devices", Korean Conference on Semiconductors, Gangwon, South Korea, (2025).
양웅기, 이현지, 짠 다이 드엉, 허재영, “블록 단위 변환 색인 버퍼 병합에 대한 성능 실험”, 대한전자공학회 하계종합학술대회, 포스터, 롯데호텔 서귀포, 26-28 June 2024.
김민준, 강호준, 강대윤, 짠 다이 드엉, 허재영, “선형 타일 주소 변환기 하드웨어 구현”, 대한전자공학회 하계종합학술대회, 포스터, 롯데호텔 서귀포, 26-28 June 2024
Tran Dai Duong and Jae Young Hur, "TLB Coalescing using Page Table Compression", Korean Conference on Semiconductors, Gyeongju, South Korea, (2024).
Tran Dai Duong and Jae Young Hur, "TLB Coalescing using Page Table Compression", Summer Annual Conference of IEIE, Seogwipo, South Korea, 2023, pp. 761-762.
Tran Dai Duong, Yung-Cheol Byun, and Jae Young Hur, "Flexible Physical Memory Allocator for TLB Coalescing in System on Chip", Korean Conference on Semiconductors, Gangwon, South Korea, (2023).
D. D. Tran, T. T. Le, M. T. Duong, M. Q. Pham, and M. S. Nguyen, "FPGA Design for Deep Q-Network: A case study in Cartpole Environment," 2022 International Conference on Multimedia Analysis and Pattern Recognition (MAPR), Phu Quoc, Vietnam, 2022, pp. 1-6, doi: 10.1109/MAPR56351.2022.9925007.
D. D. Tran, T. G. Truong, T. G. Do and T. D. Do, "Risc-V Random Test Generator," 2021 15th International Conference on Advanced Computing and Applications (ACOMP), Ho Chi Minh City, Vietnam, 2021, pp. 150-155, doi: 10.1109/ACOMP53746.2021.00027.

Patent

허재영, 변영철, 짠 다이 드엉, "버디 메모리 할당 방법", 10-2841993, 2025년 7월 30일
허재영, 짠 다이 드엉, 변영철, "페이지 사이즈를 고려한 메모리 할당을 수행하는 메모리 관리 시스템 및 메모리 관리 방법", 10-2792915, 2025년 4월 3일

Textbook

Nguyễn Minh Sơn, Phan Đình Duy, Hồ Ngọc Diễm, Trần Đại Dương, Nguyễn Duy Xuân Bách, Hà Lê Hoài Trung, Lầu Phi Tường, Nguyễn Thanh Thiện, Trương Văn Cương, "Computer Architecture", VNUHCMPRESS, 2023 (Vietnamese)
Lâm Đức Khải, Trần Đại Dương, "Practical guide to Digital Logic Design", VNUHCMPRESS, 2021 (Vietnamese)
Lâm Đức Khải, Trần Đại Dương, "Practical guide to Digital Circuits", VNUHCMPRESS, 2021 (Vietnamese)
Lâm Đức Khải, Hồ Ngọc Diễm, Trần Đại Dương, "Digital Logic Design 2", VNUHCMPRESS, 2019 (Vietnamese)
Phan Đình Duy, Nguyễn Thanh Thiện, Trần Đại Dương, Trần Hoàng Lộc, "Practical guide to Operating Systems", VNUHCMPRESS, 2018 (Vietnamese)

Work experience

[2018] - [now]

Instructor

Teaching Digital Circuits, Digital Logic Design, Digital System Design with Verilog HDL, Computer Architecture, Electronic Devices and Circuits, Digital CMOS IC Design, Operating Systems

University of Information Technology, VNUHCM, Vietnam

[2015] - [2017]

Hardware Design Engineer

Functional Design and Verification

Renesas Design Vietnam Co., Ltd., Vietnam

[2015]

Analog+1 Intern

Full CMOS Analog Design Flow

Integrated Circuit Design Research & Education Center (ICDREC), VNUHCM, Vietnam

[2014]

Hardware Design Intern

Full Standard cell based Digital Front-end Design Flow

Renesas Design Vietnam Co., Ltd., Vietnam

Education

[2022] - [now]

Combined Masters and PhD in Electronic Engineering

Research in Embedded SytemsSytems and Computer Architecture

Jeju National University, South Korea

[2011] - [2016]

Bachelor of Engineering in Computer Engineering

The best graduation student in Computer Engineering, focus on IC Design & Hardware

University of Information Technology, VNUHCM, Vietnam

Contacts

Email: duong.uitce@gmail.com
Zalo (Vietnam): 0762064857
Kakao (Korea): DaiDuong

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