Verilog DMR ARM7

■ mini ARM7

• ARM7 compatible uP

• 4 stage pipeline & 24 instruction set

• Cell count: 17813(spartan3 FPGA)

■ TMR mini ARM7

• • Fault tolerant mechanism: Triple modulo redundant Majority voter, Forwar Recovery

• Cell count: 53685(spartan3 FPGA)

■ Forward Recovery DMR (FRD) mini ARM7

• Fault tolerant mechanism: Forward recovery DMR, 2 checkers

• Cell count: 35911 (spartan3 FPGA)

■ Backward recovery DMR mini ARM7

• Fault tolerant mechanism: Backward recovery DMR, 1checker & checkpoint

• Cell count: 38269(spartan3 FPGA)