Search this site
Embedded Files
Skip to main content
Skip to navigation
Dependable Systems Lab.
Dependable Systems Lab.
About DSLab
0. 안전 필수 시스템
신인성 (Dependability) 정의
안전 필수 시스템 정의
1. 산업/경제 현황
2. 기술 현황
3. 연구 목적 및 목표
4. 연구 내용
5. 연구 계획
DES뉴스
Knowhere
dependability
Fault-Error-Failure101
Reliability
Safety
Validation
Verification & verification 검증 & 확인
Hazard-Risk101
UAM/AAV
Embedded Systems
Functional Safety
Functional Safety Books
International functional safety standards
Space
NEWS -사업산업
NEWS-EVERYDAY
NEWS-안전
Risk analysis
Sensors
Simulations
Aircraft simulation
SW Testing
System Safety
Unclassified
고장 사례 모음
스마트 리빙
Security Facts
Security Facts
Lectures
People
Advisor
Academic activities
Professional activities
Alumni
Recruitment
Researchers
김주영
김진실
문성엽
백경민
유재웅
이동우
이재용
Projects
Current projects
Finished projects
Planning projects
Drone Cam for outdoor long take
Safe Software Design Development
Publications
Research Topics
1. Avionics
1. 항공 임베디드 시스템 개발 방법
1.항공 임베디드 시스템 개발 방법
1.TCAS Integrated Simulator
2.Sense and Avoid
3.Air Data Computer
4.Remote Data Concentrator
5.Integrated Modular Architecture
GCS+Xplane
References_Avionics
Simulink+FlightGear
Simulink+Stateflow+Scade+DMR+Xplane
Simulink+Stateflow+XPlane
UAV Simulation Demonstration
2. Dependability
Dependability assurance
deterministic fault injection
fault-injection
statistical fault injection
Fault-injection
reliability prediction
3. Fault processing
Fault avoidance
Fault tolerance
4. Fault tolerant systems
FT components
SystemC target
SystemC DMR ARM7
SystemC DMR MIPS 4K
Verilog target
Verilog DMR ARM7
Verilog DMR OpenRISC
FT systems
DMR using Opensource HW
HILS target
신뢰성 분석
결함감내 시스템
5. Drone applications
drone paper review
2016 IEEE/AIAA 35th DASC
6. Rehabilitation
7. Smart Digital Signage
age recognition digital signage
digital signage links
gender recognition digital signage
face swap digital signage
mobile digital signage
8. Research papers plan
Useful Links
UML online lecture
Dependable Systems Lab.
FT components
System-level Targets:
SystemC target
Register-level Targets:
Verilog target
Google Sites
Report abuse
Page details
Page updated
Google Sites
Report abuse