EDAthon 2026

Problem Descriptions

Problem 1:  RTL Code Completion

RTL design is the starting point of most digital integrated circuit design flows. Designers describe the behavior of a hardware module using languages such as Verilog or SystemVerilog, and the RTL code is later simulated, synthesized, and implemented by downstream EDA tools. However, writing correct RTL is often tedious: even small mistakes in signal width, control logic, reset behavior, or state transitions can cause simulation failures.

In this problem, contestants will work on RTL code completion tasks derived from the CVDP benchmark. Each task provides a natural-language description, starter RTL code, metadata, and a simulation-based testbench. The target RTL files contain partial code, and the goal is to complete or modify the implementation so that the design satisfies the specification and passes the provided tests.

The evaluation will be based on functional correctness. Contestants may use AI agents to inspect the prompt, read the RTL files, run the testbench, analyze simulation failures, and iteratively improve the code. The final submission should contain the completed RTL implementation for each task.

Reference:

[1] Pinckney, Nathaniel, et al. "Comprehensive Verilog design problems: A next-generation benchmark dataset for evaluating large language models and agents on rtl design and verification." arXiv preprint arXiv:2506.14074 (2025).

Problem 2: PPA-Aware RTL Optimization

After an RTL design is functionally correct, designers often need to optimize it for PPA: power, performance, and area. Different RTL implementations of the same behavior may lead to very different synthesis results. For example, a design with unnecessary registers, redundant logic, or inefficient arithmetic expressions may pass all functional tests but still produce a larger or slower circuit.

In this problem, contestants will work on RTL optimization tasks derived from the Pluto benchmark. Each task provides a behavior description, a required module interface, an unoptimized reference implementation, and a testbench. The goal is to implement an optimized module that preserves the same behavior as the reference design while improving the hardware quality after synthesis.

The submissions will first be checked for functional correctness using simulation. Correct designs will then be evaluated using synthesis-based PPA metrics such as area, timing, and power. Contestants are encouraged to use AI agents to understand the reference design, rewrite the RTL, run simulation and synthesis tools, and search for better implementations.

Reference:

[1] Abdelatty, Manar, et al. "Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code." arXiv preprint arXiv:2510.14756 (2025).

Problem 3:  Global Routing Closure

Physical design transforms a synthesized netlist into a physical layout. After placement and clock tree synthesis, global routing estimates how wires should be routed across the chip and checks whether the available routing resources are sufficient. If the design is too congested, the global router may report overflow, meaning that some regions require more routing resources than available

In this problem, contestants will work on global routing closure tasks derived from ChiPBench. Each task starts from a frozen post-CTS design state. The placement and clock tree are already fixed, and contestants are not required to rerun the full physical design flow. Instead, they will tune the global routing configuration to reduce congestion and help the design complete global routing successfully.

For each design, contestants will be given the post-CTS design database, timing constraints, and related metadata. The expected submission is a Tcl configuration file used before global routing. The evaluation will focus on routing overflow, congestion, wirelength, via count, and possible timing or power side effects. The main objective is to turn difficult congested cases into routable designs while maintaining good routing quality.

Reference:

[1] Wang, Zhihai, et al. "Benchmarking end-to-end performance of ai-based chip placement algorithms." Advances in Neural Information Processing Systems 38 (2026).