EDAthon 2023

August 25, 2023

Hong Kong University of Science and Technology

Sponsored by Cadence; IEEE CEDA; IEEE CEDA Hong Kong Chapter; IEEE CEDA Guangzhou Chapter

Organized by Hong Kong University of Science and Technology

Photo Album:

EDAthon 2023 was held successfully offline at HKUST on Aug 25th 2023, with 25 teams participating. During the one-day competition, all 50 participants exercised their sophisticated coding and analytical skills to solve interesting EDA problems. All the awardees will get their certificates and cash prize. The six teams below were awarded for their outstanding performance. Each team can request up to HK$ 3,000 reimbursement for their travel expenses.

Champion

Tsinghua University

Students:

Jiawen Cheng & Jiechen Huang

Supervisor:

Wenjian Yu

Second Place

Peking University

Students:

Ziyun Zhang & Jieran Zhang

Supervisor:

Guojie Luo

Second Place

Chinese University of Hong Kong (Shenzhen)

Students:

Yapeng Li & Wenxu Zhang

Supervisor:

Tinghuan Chen & Zushuai Xie

Third Place

Hong Kong University of Science and Technology (Guangzhou)

Students:

Yuetong Fang & Yulong Huang

Supervisor:

Renjing Xu & Bojun Cheng

Third Place

Hong Kong University of Science and Technology (Guangzhou)

Students:

Wenji Fang & Chen Chen

Supervisor:

Hongce Zhang

Third Place

Chinese University of Hong Kong

Students:

Su Zheng & Wuqian Tang

Supervisor:

Bei Yu

EDAthon is a whole-day programming contest (9:00am-3:00pm programming + 3:30pm-4:30pm seminar) that features interesting and challenging topics in Electronic Design Automation (EDA). It is also a unique opportunity to bring together talents for EDA which enables the rapid advancement in computer technology. This year we will have an on-site contest in the Hong Kong University of Science and Technology (HKUST). The contest will involve solving interesting problems in the broad context of Computer-Aided Design (CAD) of integrated circuits and systems. It will emphasize on team work, problem solving skills and programming techniques for EDA applications. It is a goal of EDAthon and CEDA HK to promote EDA in Hong Kong and her neighboring regions, and to nurture the best of the next-generation students and professionals for the EDA community.

The contest is open to two-person teams of graduate students or senior undergraduate students currently full-time enrolled in a university, specializing in EDA or related areas. In the contest, there will be five problems selected from the following areas:

- - System Design and Analysis
  - Logic and High-level Design
  - Physical Design
  - Circuit Analysis
  - Emerging Technologies, e.g., DFM, Security, Biochip, Machine Learning in EDA etc.

During the contest, students will be given the problem statements and some sample test data. The answers will be judged based on their correctness under the given constraints using hidden benchmarks. Three teams winning the contest will be rewarded with trophies and cash prizes as follows.

First Prize (one team): 5000 HKD, supervisor (2000 HKD)
Second Prize (two teams): 3000 HKD, supervisor (1000 HKD)
Third Prize (three teams): 2000 HKD, supervisor (500 HKD)

IMPORTANT DATES

June 2023: Call for participation released, open for enrollment emails
July 2023: Registration deadline

Registration

Please complete the following Tencent form for registration.

Schedule

9am-3pm: EDAthon2023 Contest

3:00-3:30pm: Break

3:30-5:00pm: Mini-seminar on the contest problems

After 6:30pm: Dinner

Problem Descriptions

Problem 1: Cell Placement Legalization

This problem is to legalize single- and double-row height cell placement in two rows under the presence of blockages. Given the initial cell positions and the relative position of every pair of same-row cells, you need to find a legal placement result with minimized total displacement. There will also be several blockages that need to be avoided.

Reference:

[1] Stefan Hougardy, Meike Neuwohner, and Ulrike Schorr. "A Fast Optimal Double Row Legalization Algorithm" In Proceedings of the 2021 International Symposium on Physical Design.

Problem 2: DNN mapping in CIM architecture

Compute-in-Memory (CIM) has emerged as a promising technique for Deep Neural Network (DNN) acceleration, owing to its high energy efficiency. It employs the cross-bar structure to perform Vector Matrix Multiplication (VMM) operations in the mixed-signal domain. However, non-idealities of devices and circuits necessitate verifications of software performance prior to the real hardware implementation of CIM architecture. In this problem, you are required to simulate the Convolutional Neural Network (CNN) operation mapped to the CIM array, considering a limited device on-off ratio and ADC quantization loss.

Reference:

[1] X. Peng, R. Liu, and S. Yu. "Optimizing weight mapping and data flow for convolutional neural networks on processing-in-memory architectures." IEEE Transactions on Circuits and Systems I: Regular Papers 67.4 (2019): 1333-1343.

[2] X. Peng, S. Huang, Y. Luo, X. Sun and S. Yu, "DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 32.5.1-32.5.4, doi: 10.1109/IEDM19573.2019.8993491.

[3] S. Huang, H. Jiang, and S. Yu. "Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators." ACM Transactions on Design Automation of Electronic Systems 28.3 (2022): 1-23.

Problem 3: Digital Filter Design

Digital filters are widely used in practical circuit design, such as PLLs, Class D amplifiers, and so on. Designers of digital filters can quickly build the hardware circuit of the filter by knowing its transfer function (H(z) = ...): in the transfer function, the "z^-1" operator in the frequency domain represents a time delay of one sampling time unit in the time domain. Therefore, circuit designers can implement the desired transfer function by adding a delay circuit, adders, and multipliers. The requirements presented by customers for digital filters are the frequency response characteristics of the filter (pass and stop frequency parameters, as well as attenuation parameter characteristics). Our question is: how to calculate the transfer function from the frequency response characteristics.

Reference:

[1] https://en.wikipedia.org/wiki/Butterworth_filter

Problem 4: Power/Ground Mesh Routing with Interleaving Bump Distribution

In advanced packaging, the bumps above an interposer are connected from micro bumps to the C4 bumps above the substrate. The purpose of this problem is to simulate the behavior during the routing of advanced packaging.

There is a step in the advanced packaging process, which will generate a PG mesh for many power/ground bumps and connect these bumps together. With the different distribution of these bumps, there will be different situations to be dealt with in the automated routing. The situation to be faced in this problem is that the bumps closest to the x-direction and y-direction of the bump are connected to different nets, and the purpose of this problem is to construct an automated routing algorithm satisfying this situation.

Reference:

[1] CCF DL Focus On Integrated Circuit Design, https://www.ccf.org.cn/ccfdl/ccf_dl_focus/Integrated_Circuit_Design/vlume2/

[2] Don Scansen, "AMD分享Chiplet设计案例", https://www.ednchina.com/news/202103111111.html

[3] https://new.qq.com/rain/a/20220905A083LG00

Problem 5: H-Tree Generation for Clock Mesh Network

Appropriate clock distribution is critical for the design of efficient low-power circuits; while clock mesh topologies are resistant to skew variations, the computationally expensive simulation effort, coupled with multidimensional dependencies with clock drivers, pre-mesh tree structure, RC-aware buffering, load distribution, and wirelength, complicates the algorithmic design of clock mesh network structures. The symmetric layout, scalability, and overall low-power consumption of H-Trees compel it to be a popular design choice for clock meshes.

Through data-efficient modelling and intelligent optimization, create an automated H-Tree generator for clock mesh networks.

References:

[1] Zhou, Nancy Y., et al. "Pacman: Driving nonuniform clock grid loads for low-skew robust clock network." Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop. 2014.

[2] Jackson, Michael AB, Arvind Srinivasan, and Ernest S. Kuh. "Clock routing for high- performance ICs." Proceedings of the 27th ACM/IEEE Design Automation Conference. 1991.

[3] Chao, Ting-Hai, et al. "Zero skew clock routing with minimum wirelength." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 39.11 (1992): 799-814.

[4] Tsay, R-S. "An exact zero-skew clock routing algorithm." IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems 12.2 (1993): 242-249.