EDAthon 2017

July 28, 2017

The Chinese University of Hong Kong, Shatin, Hong Kong

Sponsored by IEEE CEDA, Organized by IEEE CEDA Hong Kong Chapter

Co-organized by

Dept. of CSE of CUHK, Dept. of EEE of HKU,

Dept. of CS of CityU, Dept. of COMP of PolyU, Dept. of ECE of HKUST

The exciting EDAthon 2017 contest, organized by CEDA HK Chapter, was held on July 28 of 2017 with the participation of 10 teams from Mainland China, Taiwan and Hong Kong. During the one-day competition, all the participants displayed impressive EDA skills and the following three teams were awarded for their outstanding performance.

Champion

National Taiwan University

Students: Cheng-Han Yang and Chia-Lin Hsieh

Supervisor: Dr. Chung-Yang (Ric) Huang

Second Place

Tsinghua University

Students: Wenyu Sun and Yixiong Yang

Supervisor: Dr. Yongpan Liu

Third Place

Peking University

Students: Feng Wang and Jiaxi Zhang

Supervisor: Dr. Luo Guojie

More photos:

Album: EDAthon 2017 - CEDA HK

EDAthon is a whole-day programming competition with focuses on interesting and challenging problems in Electronic Design Automation (EDA). The contest will focus on interesting problems related to VLSI Computer-Aided Design. It will emphasize on team work, problem solving skills and programming techniques for EDA applications. It is a goal of EDAthon to promote EDA in Hong Kong and in nearby regions, and to nurture the best of the next generation of students and professionals in the EDA field. This is a unique opportunity to bring together talents for EDA which enables the rapid advancement in computer technology.

The contest is open to two-person teams of graduate students or senior undergraduate students currently full-time enrolled in a university, specializing in EDA or related areas. Partial or full travelling grants will be provided. Teams will be selected based on their academic backgrounds and their relevant EDA programming experiences. In the contest, there will be five problems selected from the following areas:

System Design and Analysis
Logic and High-level Design
Physical Design
Circuit Analysis
Emerging Technologies, e.g., DFM, Security, Biochip

During the contest, students will be given the problem statements and some sample testing data. The answers will be judged based on their correctness under the given constraints using hidden benchmarks. The teams winning the contest will be rewarded with trophies and cash prizes.

IMPORTANT DATES

Registration Deadline ~~May 26, 2017~~ (Extended)
Notification of Contest Participation May 31, 2017
Posting of Relevant Research Papers: Posted below.
Contest July 28, 2017

Relevant Research Papers

H. Zhuang, S.-H. Weng, C.-K. Cheng. Power Grid Simulation Using Matrix Exponential Method with Rational Krylov Subspaces. ASICON. 2013. [Link]
S.-H. Weng, Q. Chen, C.-K. Cheng. Time-domain analysis of large-scale circuits by matrix exponential method with adaptive control. TCAD. 2012. [Link]
C. Yang, M. Ciesielski. BDS: A BDD-based Logic Optimization System. IEEE TCAD. 2002. [Link]
N. Vemuri, P. Kalla, R. Tessier. BDD-based logic Synthesis for LUT-based FPGAs. ACM TODAES. 2002. [Link]
Z. Qin, Y. Wang, D. Liu, Z. Shao. Real-time flash translation layer for NAND flash memory storage systems. RTAS. 2012. [Link]
Y. Wang, Z. Qin, R. Chen, Z. Shao, Q. Wang, S. Li, L. T. Yang. A Real-time Flash Translation Layer for NAND Flash Memory Storage Systems. TMSCS. 2016. [Link]
B. Yu, D. Liu, S. Chowdhury, D. Z. Pan. TILA: Timing-driven Incremental Layer Assignment. ICCAD. 2015. [Link]
B. Yu, X. Xu, J.-R. Gao, Y. Lin, Z. Li, C. J. Alpert, D. Z. Pan. Methodology for standard cell compliance and detailed placement for triple patterning lithography. TCAD. 2015. [Link]
H. Kong, T. Yan, M. D. Wong, M. M. Ozdal. Optimal Bus Sequencing for Escape Routing in Dense PCBs. ICCAD. 2007. [Link]