EDAthon 2022

Problem 1: Post-Implementation Metric Estimation via Neural Tangent Kernel (NTK)

High-level synthesis (HLS) tools automate the conversion of C/C++/SystemC-based specifications to hardware description languages such as Verilog or VHDL, significantly increasing productivity in customized hardware design. HLS tool reports can convey important data such as expected performance, timing, resource usage, and composition of the synthesized register-transfer-level (RTL) design. However, the reported values are highly inaccurate. Machine learning (ML) techniques have been used to improve HLS tools in order to obtain accurate estimated results. The recent Neural Tangent Kernel (NTK), arising from deep learning theory, is a specific kernel corresponding to training a linearization of a neural network. As the widths of hidden layers approach infinity, solving kernel regression with the NTK is identical to training all layers of a neural network. NTK can be efficiently computed in closed form in terms of dual activation functions when certain conditions are met. Together with the latest fast kernel regression solver EigenPro, high-quality estimations of post-implementation metrics can be obtained in a matter of seconds using only CPU.

Reference:

[1] Ma, S., & Belkin, M. "Diving into the shallows: a computational perspective on large-scale shallow learning." Advances in neural information processing systems (NeurIPS), 2017.

[2] Radhakrishnan, A. "6.S088 Modern Machine Learning: Simple Methods that Work" [Lecture 5], 2022. Retrieved from https://web.mit.edu/modernml/course/

[3] Dai, S., Zhou, Y., Zhang, H., Ustun, E., Young, E. F., & Zhang, Z. "Fast and accurate estimation of quality of results in high-level synthesis with machine learning." In IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2018. (Codes : https://github.com/cornell-zhang/quickest).

[4] Huang, G., Hu, J., He, Y., Liu, J., Ma, M., Shen, Z., ... & Wang, Y. "Machine learning for electronic design automation: A survey." ACM Transactions on Design Automation of Electronic Systems (TODAES), 2021.

Problem 2: Layout Hotspot Detection with Machine Learning Techniques

Constant scaling and reduction in feature sizes has made lithography more complex than ever before [1]. Even with various resolution enhancement techniques (RETs), manufacturing defects are still likely to happen for some sensitive layout patterns (a.k.a, hotspots), thus detecting and avoiding lithography hotspots accurately during physical verification phase is critical for yield improvement [2]. In recent years, various machine learning (ML)-based solutions are proposed for lithography hotspot detection [1, 2]. This problem will be about developing ML models like convolutional neural networks (CNNs) to detect lithography hotspots on layouts. As a data-driven problem, a pre-processed training dataset [3] will be provided in the contest. Students will focus on developing their ML models to achieve reasonable accuracy in the testing dataset.

Reference:

[1] G. R. Reddy, K. Madkour, and Y. Makris, "Machine learning-based hotspot detection: Fallacies, pitfalls and marching orders," in International Conference on Computer-Aided Design (ICCAD), 2019.

[2] H. Yang, J. Su, Y. Zou, B. Yu, and E. F. Young, "Layout hotspot detection with feature tensor generation and deep biased learning," in Design Automation Conference (DAC), 2017.

[3] J. A. Torres, "ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suite," in International Conference on Computer-Aided Design(ICCAD), 2012.

Problem 3: Counterexample Trace Reduction

Model checking is a hardware formal verification technique that can be used to check whether given properties hold on the register-transfer-level (RTL) model without supplying any stimulus input. It essentially explores all possible input combinations. A counterexample to the property is a trace (a sequence of states) that starts from the initial state of the RTL model and reaches a states where the property evaluates to false. A technique called bounded model checking (BMC) can be used to find such a counterexample (if it does exist). A counterexample trace by default contains the assignment to all state/input variables in every clock cycle. However, some information is redundant. For example, consider a counter that runs freely:

always @(posedge clock)

counter <= counter + 1;

If the counter had value x in the previous cycle, no doubt it will turn into (x+1) in the next cycle. In a "reduced" counterexample trace, we want to remove the redundant variable assignment and only keep those that determines the execution path (the pivot).

References:

[1] Armin Biere, Alessandro Cimatti, Edmund Clarke, Yunshan Zhu, "Symbolic Model Checking without BDDs," International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), 1999, pp. 193–207.

[2] Lintao Zhang, Sharad Malik, "Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications," Design, Automation and Test in Europe Conference and Exhibition (DATE), 2003, pp. 880-885.

Problem 4: Neural architectural search for RRAM- based AI accelerator

RRAM-based in-memory computing is a promising technique to accelerate future AI. It employs a matrix of RRAM, or tunable resistors, to perform vector-matrix multiplications using Ohm’s law and Kirchhoff’s law. (e.g. Fig. 7a of Ref. [1])

However, mapping neural networks to a memristor array involves partition the array into non- overlapping sub-arrays, where each sub-array implements either one convolutional layer or a dense layer. [2] How to maximize the network performance on a given dataset subject to this hardware constraint is a tough optimization question.

Neural architectural search (NAS) provides an efficient way to figure out networks that maximize the performance of a task. [3] So in this problem, you are encouraged to employ NAS to design a convolutional neural network for a N×N (e.g. N=256 gives 64k weights, you can ignore differential pairs in representing negative weights at your wish.) RRAM array to classify MNIST dataset.

References:

[1] Wang, Z., Wu, H., Burr, G.W. et al. "Resistive switching materials for information processing," Nat Rev Mater 5, 2020. https://doi.org/10.1038/s41578-019-0159-3

[2] Wang, Z., Li, C., Lin, P. et al. "In situ training of feed-forward and recurrent convolutional memristor networks," Nat Mach Intell 1, 2019. https://doi.org/10.1038/s42256-019-0089-1

[3] Zhang, L. L., Yang, Y., Jiang, Y., "Fast Hardware-Aware Neural Architecture Search," 2019. https://arxiv.org/abs/1910.11609