EDAthon 2025

December 1st, 2025

Hong Kong University of Science and Technology

Sponsored by Cadence; UniVista; HiSilicon; IEEE CEDA; IEEE CEDA Hong Kong Chapter; IEEE CEDA Guangzhou Chapter

Organized by Hong Kong University of Science and Technology

The EDAthon 2025 (EDA programming contest) will be held offline at HKUST on Dec 1st (Mon) 2025. Each non-local team can request reimbursement (the specific amount TBD, at least HK$ 2000) for their travel expenses.

EDAthon is a whole-day programming contest (9:00am-3:00pm programming + 3:30pm-5:00pm seminar) that features interesting and challenging topics in Electronic Design Automation (EDA). It is also a unique opportunity to bring together talents for EDA which enables the rapid advancement in computer technology. This year we will have an on-site contest in the Hong Kong University of Science and Technology (HKUST). The contest will involve solving interesting problems in the broad context of Computer-Aided Design (CAD) of integrated circuits and systems. It will emphasize on team work, problem solving skills and programming techniques for EDA applications. It is a goal of EDAthon and CEDA HK to promote EDA in Hong Kong and her neighboring regions, and to nurture the best of the next-generation students and professionals for the EDA community.

The contest is open to two-person teams of graduate students or senior undergraduate students currently full-time enrolled in a university, specializing in EDA or related areas. In the contest, there will be at least five problems selected from the following areas:

- - System Design and Analysis
  - Logic and High-level Design
  - Physical Design
  - Circuit Analysis
  - Emerging Technologies, e.g., DFM, Security, Biochip, Machine Learning in EDA etc.

During the contest, students will be given the problem statements and some sample test data. The answers will be judged based on their correctness under the given constraints using hidden benchmarks. Three to six teams winning the contest will be rewarded with certificate and cash prizes (amount TBD).

IMPORTANT DATES

Sep 9th, 2025: Call for participation released, open for enrollment
Oct 31st, 2025: Registration deadline

Registration

Please complete the following Tencent form for registration:

https://wj.qq.com/s2/23517126/8iee/

Schedule

9am-3pm: EDAthon2025 Contest

3:00-3:30pm: Break

3:30-5:00pm: Mini-seminar on the contest problems

Problem Descriptions

Problem 1: Resubstitution in 3-Valued Logic

Resubstitution is a method for logic optimization. It works on a logic network, which is a directed acyclic graph (DAG) where each node represents a combinational logic gate (such as AND, OR, NOT). Resubstitution operates on one node at a time in this DAG and tries to figure out if the logic function of this node can be represented by a function of a set of other nodes.

For example, for a logic network with 3 primary inputs (a, b, c) and 3 other nodes (n1, n2, n3). Suppose the logic functions of n1, n2, n3 are as follows:

n1 = a + c

n2 = b + c

n3 = ab + c

where `+` means logic OR. `ab` means `a AND b`. The logic of n3 can be represented by a function of n1 and n2. Namely, n3 = (a+c)(b+c) = n1 n2. By replacing n3 with the function of n1 and n2, we can reuse existing logic and hopefully reduce the area cost of the logic circuit.

Now, the objective of this question is to decide, for a given logic network with multiple primary outputs, whether we can represent the logic of the last output as a function of all other outputs. Specifically, we consider 3-valued logic, where the three possible values are represented as 0, 1, and 2.

Logic networks will be given in the BENCH format and the logic function of logic gates will be given as truth tables. The parsers for these formats will be provided, so the contestants only need to focus on the algorithm that decides the possibility of resubstitution.

Reference:

[1] Three-Valued Logic. [https://en.wikipedia.org/wiki/Three-valued_logic](https://en.wikipedia.org/wiki/Three-valued_logic)

[2] Using Simulation and Satisfiability to Compute Flexibilities in Boolean Networks. Alan Mishchenko et al. TCAD 2006, vol.25, no.5, pp.743-755. [https://people.eecs.berkeley.edu/~alanmi/publications/2005/tcad05_s&s.pdf](https://people.eecs.berkeley.edu/~alanmi/publications/2005/tcad05_s&s.pdf)

Problem 2: Routing for Microfluidic Devices

The ISO 22916:2022 standard provides a standardized description for microfluidic devices consisting of a main chip board and multiple modules. Fig. 1 shows an example of a microfluidic chip.

Given a microfluidic device with placed modules, this problem asks to route as many channels as possible without violating the ISO 22916:2022 standard. The main constraints are summarized as follows.

• The number of waypoints of a routed channel should be smaller than a specified number.

• Segments of different channels should not overlap.

• There are minimum spacing constraints between segments and between segments and waypoints. Please refer to [1] for detailed descriptions of all constraints.

Reference:

[1] P. Ebner and R. Wille, ”Automatic Validation and Design of Microfluidic Devices Following the ISO 22916 Standard,” 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, TN, USA, 2024, pp. 278- 283, doi: 10.1109/ISVLSI61997.2024.00058.

Problem 3: Efficient Expressions Evaluation

In complex Virtuoso IC design flow, there are thousands of circuit and model parameters and complex expressions in the design. To simulate the circuit, the expression evaluation is normally time-consuming. And in most cases, these circuit and model parameters have dependencies on each other, making the expression evaluation even more complex. Meanwhile, in many situations, it is necessary to re-evaluate all the expressions by changing only very few parameters. There is a good opportunity for EDA tools to efficiently do expression evaluation without wasted expression calculation and accuracy loss.

For example, the value of variable B has a dependency to variable A. And users will need to take the value of variable A into account of variable B when evaluating variable B. This is a very common usage in the circuit design / simulations, like this simple case:

A = var1 + 2;

B = A/2;

C = B>1.0 ? var1 : A;

EDA tool needs an efficient way to calculate them in an optimized order, to get the correct result without duplicated/wasted calculations.

Problem 4: Find Dominant Devices of a Circuit

Statistical library models are essential for performing static timing analysis (STA) in digital circuits. These models are typically generated by analyzing how sensitivity parameters influence the delay arc measurements of each MOS device in the circuit. However, applying this iterative approach to every MOS is inefficient and impractical for production environments.

To enhance efficiency, we propose identifying the dominant MOS devices that significantly impact the current delay arc prior to running full simulations. This targeted strategy reduces the number of required simulations and substantially accelerates the overall library characterization process. Accurately identifying these dominant MOS devices is, therefore, a critical step in building effective statistical library models.

Reference:

[1] https://www.cadence.com/en_US/home/resources/white-papers/liberate-characterization-portfolio-wp.html