Embedded Files
Link to datasheet
High performance RISC CPU
• All single cycle instructions except for program branches which are two cycle
One instruction cycle consists of four oscillator periods.
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
For an oscillator frequency of 4 MHz, the normal instruction execution time is 1 us.
• Interrupt capability (up to 14 sources)
• Eight level deep hardware stack
• Selectable oscillator options
• Low power, high speed CMOS FLASH/EEPROM technology
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
Peripheral Features (only those we are going to use) :
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 10-bit multi-channel Analog-to-Digital converter
• Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection
• Synchronous Serial Port (SSP) with SPI (Master mode) and I2C (Master/Slave)
• Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls
Pins
OSC1/CLKIN - Oscillator crystal input/external clock source input. This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
OSC2/CLKOUT - Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
MCLR/VPP - Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device.
RA0/AN0 - Digital input/output - RA0 can also be analog input0.
RA1/AN1 - Digital input/output - RA1 can also be analog input1.
RA2/AN2/VREF- - Digital input/output - RA2 can also be analog input2 or negative analog reference voltage.
RA3/AN3/VREF+ - Digital input/output - RA3 can also be analog input3 or positive analog reference voltage.
RA4/T0CKI - Digital input/output - RA4 can also be the clock input to the Timer0 module. Output is open drain type.
RA5/SS/AN4 - Digital input/output - RA5 can also be analog input4 or the slave select for the synchronous serial port.
RB0/INT - Digital input/output with programmable internal weak pull-up on input - RB0 can also be the external interrupt pin.
RB1 - Digital input/output with programmable internal weak pull-up on input
RB2 - Digital input/output with programmable internal weak pull-up on input
RB3/PGM - Digital input/output with programmable internal weak pull-up on input - RB3 can also be the low voltage programming input.
RB4 - Digital input/output with programmable internal weak pull-up on input - Interrupt-on-change pin.
RB5 - Digital input/output with programmable internal weak pull-up on input - Interrupt-on-change pin.
RB6/PGC - Digital input/output with programmable internal weak pull-up on input - Interrupt-on-change pin or In-Circuit - Debugger pin - Serial programming clock
RB7/PGD - Digital input/output with programmable internal weak pull-up on input - Interrupt-on-change pin or In-Circuit - Debugger pin - Serial programming data.
RC0/T1OSO/T1CKI - Digital input/output - RC0 can also be the Timer1 oscillator output or Timer1 clock input
RC1/T1OSI/CCP2 - Digital input/output - RC1 can also be the Timer1 oscillator input or Capture2input/Compare2 output/PWM2 output.
RC2/CCP1 - Digital input/output - RC2 can also be the Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL - Digital input/output - RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes.
RC4/SDI/SDA - Digital input/output - RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO - RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK - Digital input/output - RC6 can also be the USART Asynchronous Transmit or Synchronous Clock.
RC7/RX/DT - Digital input/output - RC7 can also be the USART Asynchronous Receive or Synchronous Data.
VSS - Ground reference for logic and I/O pins.
VDD - Positive supply for logic and I/O pins.
All next pins are for PIC16F877
RD0/PSP0 - Digital input/output - parallel slave port bit0 when interfacing to a microprocessor bus.
RD1/PSP1 - Digital input/output - part of parallel slave port bit1 when interfacing to a microprocessor bus.
RD2/PSP2 - Digital input/output - part of parallel slave port bit2 when interfacing to a microprocessor bus.
RD3/PSP3 - Digital input/output - part of parallel slave port bit3 when interfacing to a microprocessor bus.
RD4/PSP4 - Digital input/output - part of parallel slave port bit4 when interfacing to a microprocessor bus.
RD5/PSP5 - Digital input/output - part of parallel slave port bit5 when interfacing to a microprocessor bus.
RD6/PSP6 - Digital input/output - part of parallel slave port bit6 when interfacing to a microprocessor bus.
RD7/PSP7 - Digital input/output - part of parallel slave port bit7 when interfacing to a microprocessor bus.
RE0/RD/AN5 - Digital input/output - RE0 can also be read control for the parallel slave port, or analog input5.
RE1/WR/AN6 - Digital input/output - RE1 can also be write control for the parallel slave port, or analog input6.
RE2/CS/AN7 - Digital input/output - RE2 can also be select control for the parallel slave port, or analog input7.
Memory organization
Program memory (FLASH)
Data memory (RAM)
STATUS REGISTER (bank0)
The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5
RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
OPTION_REG Register
The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB.
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
INTCON Register
The INTCON Register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software).
0 = None of the RB7:RB4 pins have changed state
PIE1 Register
The PIE1 register contains the individual enable bits for the peripheral interrupts.
bit 7
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
PIR1 Register
The PIR1 register contains the individual flag bits for the peripheral interrupts.
bit 7
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are:
• SPI
- A transmission/reception has taken place.
• I2C Slave
- A transmission/reception has taken place.
• I2C Master
- A transmission/reception has taken place.
- The initiated START condition was completed by the SSP module.
- The initiated STOP condition was completed by the SSP module.
- The initiated Restart condition was completed by the SSP module.
- The initiated Acknowledge condition was completed by the SSP module.
- A START condition occurred while the SSP module was idle (Multi-Master system).
- A STOP condition occurred while the SSP module was idle (Multi-Master system).
0 = No SSP interrupt condition has occurred.
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
PIE2 Register
The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, and the EEPROM write operation interrupt.
bit 7
Unimplemented: Read as '0'
bit 6
Reserved: Always maintain this bit clear
bit 5
Unimplemented: Read as '0'
bit 4
EEIE: EEPROM Write Operation Interrupt Enable
1 = Enable EE Write Interrupt
0 = Disable EE Write Interrupt
bit 3
BCLIE: Bus Collision Interrupt Enable
1 = Enable Bus Collision Interrupt
0 = Disable Bus Collision Interrupt
bit 2-1
Unimplemented: Read as '0'
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
PIR2 Register
The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the EEPROM write operation interrupt.
bit 7
Unimplemented: Read as '0'
bit 6
Reserved: Always maintain this bit clear
bit 5
Unimplemented: Read as '0'
bit 4
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP, when configured for I2C Master mode
0 = No bus collision has occurred
bit 2-1
Unimplemented: Read as '0'
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused
Porte I/O
ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
ADCON0 Register
bit 7-6
ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from the internal A/D module RC oscillator)
bit 5-3
CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 4, (RA5/AN4)
101 = channel 5, (RE0/AN5)(1)
110 = channel 6, (RE1/AN6)(1)
111 = channel 7, (RE2/AN7)(1)
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D
conversion is complete)
bit 1
Unimplemented: Read as '0'
bit 0
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shut-off and consumes no operating current
ADCON1 Register
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
bit 6-4
Unimplemented: Read as '0'
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion.
The ADRESH:ADRESL registers contain the 10-bit result of the A/D conversion. When the A/D conversion is complete, the result is loaded into this A/D result register pair, the GO/DONE bit (ADCON0<2>) is cleared and the A/D interrupt flag bit ADIF is set.
These steps should be followed for doing an A/D Conversion:
1. Configure the A/D module:
• Configure analog pins/voltage reference and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared (with interrupts enabled);
OR
• Waiting for the A/D interrupt
6. Read A/D result register pair (ADRESH:ADRESL), clear bit ADIF if required.
7. For the next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before the next acquisition starts.
TAD = 2 TOSC if ADCS1:ADCS0=00
If FOSC=4MHz then TOSC=0.25us, TAD=0.5us.
CAPTURE/COMPARE/PWM MODULES
Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
CCP1CON Register
CCP2CON Register
bit 7-6
Unimplemented: Read as '0'
bit 5-4
CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1; CCP2
resets TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx = PWM mode
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The type of event is configured by control bits CCP1M3:CCP1M0 (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new value.
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set.
PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output.
A PWM output has a time-base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following
formula: PWM period = [(PR2) + 1] • 4 • TOSC • (TMR2 prescale value)
When TMR2 is equal to PR2, the following three events occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into CCPR1H
The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time:
PWM duty cycle =(CCPR1L:CCP1CON<5:4>) • TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitch-free PWM operation.
When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock, or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared.
PR2 Register
Timer2 Period Register
Example PWM frequencies
Brown-out Reset (BOR)
The configuration bit, BODEN, can enable or disable the Brown-out Reset circuit. If VDD falls below VBOR (parameter D005, about 4V) for longer than TBOR (parameter #35, about 100μS), the brown-out situation will reset the device. If VDD falls below VBOR for less than TBOR, a RESET may not occur.
Once the brown-out occurs, the device will remain in Brown-out Reset until VDD rises above VBOR. The Power-up Timer then keeps the device in RESET for TPWRT (parameter #33, about 72mS). If VDD should fall below VBOR during TPWRT, the Brown-out Reset process will restart when VDD rises above VBOR with the Power-up Timer Reset. The Power-up Timer is always enabled when the Brown-out Reset circuit is enabled, regardless of the state of the PWRT configuration bit.
CONFIGURATION WORD Register
bit 13-12 - bit 5-4
CP1:CP0: FLASH Program Memory Code Protection bits(2)
11 = Code protection off
10 = 1F00h to 1FFFh code protected (PIC16F877, 876)
10 = 0F00h to 0FFFh code protected (PIC16F874, 873)
01 = 1000h to 1FFFh code protected (PIC16F877, 876)
01 = 0800h to 0FFFh code protected (PIC16F874, 873)
00 = 0000h to 1FFFh code protected (PIC16F877, 876)
00 = 0000h to 0FFFh code protected (PIC16F874, 873)
bit 11
DEBUG: In-Circuit Debugger Mode
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger.
bit 10 Unimplemented: Read as ‘1’
bit 9
WRT: FLASH Program Memory Write Enable
1 = Unprotected program memory may be written to by EECON control
0 = Unprotected program memory may not be written to by EECON control
bit 8
CPD: Data EE Memory Code Protection
1 = Code protection off
0 = Data EEPROM memory code protected
bit 7
LVP: Low Voltage In-Circuit Serial Programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6
BODEN: Brown-out Reset Enable bit(3)
1 = BOR enabled
0 = BOR disabled
bit 3
PWRTE: Power-up Timer Enable bit(3)
1 = PWRT disabled
0 = PWRT enabled
bit 2
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
PCON Register
bit 7-2
Unimplemented: Read as '0'
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Power-On Reset (POR) Register
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details.
When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. Brown-out Reset may be used to meet the start-up conditions.
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