system_stm32f10x.h

場所はここです．

clock関係の関数を定義しています．

extern uint32_t SystemCoreClock;

extern void SystemInit(void);

extern void SystemCoreClockUpdate(void);

system_stm32f10x.cを覗いてみます．

SystemCoreClockに数値を代入しています．SystemCoreClockとはCPUとperipheralに供給する根元のclockなんでしょう．

STM32-DISCOVERYでは24MHzです．

#ifdef SYSCLK_FREQ_HSE

uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */

#elif defined SYSCLK_FREQ_24MHz

uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */

#elif defined SYSCLK_FREQ_36MHz

uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */

#elif defined SYSCLK_FREQ_48MHz

uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */

#elif defined SYSCLK_FREQ_56MHz

uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */

#elif defined SYSCLK_FREQ_72MHz

uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */

#else /*!< HSI Selected as System Clock source */

uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */

#endif

SystemInit()があります．RCCレジスタのbitをいろいろいじっています．RCCレジスタの仕様を読んでないのでどんなことをやっているのかはよくわかりません．

void SystemInit (void)

{

/* Reset the RCC clock configuration to the default reset state(for debug purpose) */

/* Set HSION bit */

RCC->CR |= (uint32_t)0x00000001;

/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */

RCC->CFGR &= (uint32_t)0xF0FF0000;

/* Reset HSEON, CSSON and PLLON bits */

RCC->CR &= (uint32_t)0xFEF6FFFF;

/* Reset HSEBYP bit */

RCC->CR &= (uint32_t)0xFFFBFFFF;

/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */

RCC->CFGR &= (uint32_t)0xFF80FFFF;

/* Disable all interrupts and clear pending bits */

RCC->CIR = 0x009F0000;

/* Reset CFGR2 register */

RCC->CFGR2 = 0x00000000;

/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */

/* Configure the Flash Latency cycles and enable prefetch buffer */

SetSysClock();

#ifdef VECT_TAB_SRAM

SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */

#else

SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */

#endif

}

SystemCoreClockUpdate()があります．レジスタの値を読んでSystemCoreClockを再計算しているようです．

void SystemCoreClockUpdate (void)

{

uint32_t tmp = 0, pllmull = 0, pllsource = 0;

uint32_t prediv1factor = 0;

/* Get SYSCLK source -------------------------------------------------------*/

tmp = RCC->CFGR & RCC_CFGR_SWS;

switch (tmp)

{

case 0x00: /* HSI used as system clock */

SystemCoreClock = HSI_VALUE;

break;

case 0x04: /* HSE used as system clock */

SystemCoreClock = HSE_VALUE;

break;

case 0x08: /* PLL used as system clock */

/* Get PLL clock source and multiplication factor ----------------------*/

pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;

pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;

pllmull = ( pllmull >> 18) + 2;

if (pllsource == 0x00)

{

/* HSI oscillator clock divided by 2 selected as PLL clock entry */

SystemCoreClock = (HSI_VALUE >> 1) * pllmull;

}

else

{

prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;

/* HSE oscillator clock selected as PREDIV1 clock entry */

SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;

}

break;

default:

SystemCoreClock = HSI_VALUE;

break;

}

/* Compute HCLK clock frequency ----------------*/

/* Get HCLK prescaler */

tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];

/* HCLK clock frequency */

SystemCoreClock >>= tmp;

}