Here's how I hooked up my LCD display to the NiosII from the previous tut. Part of the reason why I upgraded the memory to 32MB is so I have enough headroom for frame buffers. The PSP screen is quite high res (for a micro controller) with a 24 bit color resolution. In order to see what it can do I'd like to use the full color range which will require 4 Bytes per pixel (due to memory alignment, I'll get to that later) and 510KB for a full frame. Twice that for double buffered drawing.
I'll go "quickly" through the steps of
HardwareSo the basis for this new extension is going to be the previously built NiosII with SDRAM project.
Copy the folder and rename it.
Then open the project from the new folder in QuartusII and fire up SOPC builder.
Scatter-Gather DMA Controller
Avalon-ST Dual Clock FIFOTo cross the two clock domains (50Mhz RAM, 9MHz display pixel clock) and to smooth out potential memory access collisions between DMA and CPU we add a Dual clock FIFO buffer.
Pixel ConverterNow the Video Sync Generator expects to be fed with triplets of color bytes. A 24 bit symbol for each pixel. The dma controller however reads data in 4 byte chunks. Which means there is one unnecessary byte in every 32 bit word.
The Pixel Converter core just snips off that byte.
Video Sync GeneratorAnd finally we get to the Sync Generator which reads the data stream and presents the color signals to the display while also generating various sync signals.
Adding a video clockThe video sync generator and it's inputs require a clock that governs the refresh rate of the output screen, a pixel clock. Including front porches and blank periods we need to tick off 525*286 pixels and that 60 times a second (50Hz works too but lower rates will start to flicker). This results in a pixel clock of a little over 9Mhz. We have a lot of unused clocks left over in our PLL module so let's use one for this.
Wrapping upBefore we leave the SOPC builder and generate the new core lets switch the cpu back to use onchip_memory for it's program memory. Compared to onchip memory the SDRAM is actually quite slow. On top of having to service the display continuously we are also going to constantly hammer it with draw calls. It's not a bad idea to run the program from somewhere else (if possible).
Our new core should now looks like this:
Updating the symbol and pin assignmentsNow the following pin assignments obviously depend on how you connected the display to your DE0-Nano board. As an example I'll list the connections I used for my prototype board.
Next, just as before assign the pins of the Video Sync Generator by either using the Pin Planer or by editing the mynios2.qsf file (here are my assignments). Note that we are salvaging 2 pins from the LED Port for the DISP signal and the backlight. Make sure to disconnect PIN_R8 from out_port_from_the_pio_led[7] and PIN_L3 from out_port_from_the_pio_led[6].
( DE0-Nano pinout )
SoftwareHello
DMANow that we know that the core is functional we can initialize the DMA controller to send some data to the display.
We need to build a data structure in memory that tells the DMA controller what memory we want to be copied where. This structure is called a Descriptor and each Descriptor can describe a transfer of 64KB at a time. That means we need to chain a bunch of them together to transfer the entire frame buffer (480*272*4 = 522240 Bytes).
Here's a shortended version of the code with comments:
// DMA descriptors // alt_sgdma_descriptor dmaDescA[8]; alt_sgdma_descriptor dmaDescEND; // this subroutine initializes a chain of descriptors // void init_framebuffer(alt_sgdma_dev *dma) { // 480*272 lines * 4 bytes = 522240 bytes // 65532 (0xfffc) bytes * 7 = 458724 // +63516 (0xf81c) bytes // frame buffer A alt_u8* buff = (alt_u8*)frameBufferA; int i; for(i = 0; i < 8; ++i) { alt_u16 size = (i<7)?0xfffc:0xf81c; alt_avalon_sgdma_construct_mem_to_stream_desc( &dmaDescA[i], (i<7) ? (&dmaDescA[i+1]) : &dmaDescEND, (alt_u32*)buff, size, 0, i==0, i==7, 0); buff+=size; } } int main() { // initialize the DMA and get a device handle // alt_sgdma_dev *dma = alt_avalon_sgdma_open("/dev/sgdma"); // now we just continuously copy framebufferA to the Video Sync Generator // while(1) { // init the descriptors // init_framebuffer(dma); // transfer // alt_avalon_sgdma_do_sync_transfer(dma, dmaDescA); } } The complete code is here: hello_world.c1
This will effectively display the contents of the (uninitialized) memory on screen. Usually colorful garbage. Almost there!
Interrupt Service RoutineNow, our cpu is not going to be very useful if we keep it busy transferring data to the display. That's what the DMA controller is for and it can do this independently from the cpu. In fact it can be set up to run infinitely in a loop without any further cpu intervention. However, it can be very useful to be notified when a frame transfer has finished. Sometimes it is necessary to synchronize a program to the refresh rate or to switch the currently displayed memory to a different frame buffer.
This can be done with an interrupt service routine that's registered with the DMA controller and is called every time another descriptor chain has completed it's transfer.
Here's a shortened version of the program slightly modified for asynchronous DMA transfer, interrupt service routine and some drawing routines.
// The InterruptService Routine (actually a callback function called by the ISR) // void my_dma_callback(void *data) { // reset the OWNED_BY_HW bit in the descriptors to reuse the chain int i; for(i = 0; i < 8;++i) dmaDescA[i].control |= 1<<ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_OFST; // trigger another transfer all over again alt_avalon_sgdma_do_async_transfer((alt_sgdma_dev*)data, dmaDescA); } // this subroutine initializes a chain of descriptors, registers the // interrupt service routine and starts the first asynchronous transfer // void init_and_start_framebuffer(alt_sgdma_dev *dma) { // 480*272 lines * 4 bytes = 522240 bytes // 65532 (0xfffc) bytes * 7 = 458724 // +63516 (0xf81c) bytes // frame buffer A alt_u8* buff = (alt_u8*)frameBufferA; int i; for(i = 0; i < 8; ++i) { alt_u16 size = (i<7)?0xfffc:0xf81c; alt_avalon_sgdma_construct_mem_to_stream_desc( &dmaDescA[i], (i<7) ? (&dmaDescA[i+1]) : &dmaDescEND, (alt_u32*)buff, size, 0, i==0, i==7, 0); buff+= size; } dma, my_dma_callback,
ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK
|ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK,
(void*)dma);
} int main() { // switch on the backlight // IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, 64); // initialize the DMA and get a device handle // alt_sgdma_dev *dma = alt_avalon_sgdma_open("/dev/sgdma"); // assert the DISP signal // IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, 128+64);// start the DMA //init_and_start_framebuffer(dma); // now we actually have some time to draw something // Particle particles[2] = { {100,0, -1, -1}, {0, 120, -1, -1} }; Color col; int count; for(count=1;;count++) { // blink an led to see the program running (gonna be too fast to see) IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, (count & 0x0001)+128+64); // draw a line in a random color col.color8.r = rand()%256; col.color8.g = rand()%256; col.color8.b = rand()%256; line(frameBufferA, particles[0].x, particles[0].y, particles[1].x, particles[1].y, col); // bounce the particles around int i; for(i = 0; i < 2; ++i) { if(particles[i].x == 0 || particles[i].x == 479) particles[i].vx *= -1; particles[i].x += particles[i].vx; if(particles[i].y == 0 || particles[i].y == 271) particles[i].vy *= -1; particles[i].y += particles[i].vy; } } return 0; } The complete source code is here.
That's it for now. Happy drawing. Related LinksVideo Sync Generator:
Video Sync Generator and Pixel Converter Cores Scatter-Gather DMA Controller (and most other IP cores)
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