DE0-Nano | analog video
When it comes to analog circuits I'm convinced that it is all witchcraft. So the board I made reflects almost exactly TI's reference design from the datasheet.
(And yeah, it's quite obvious from the creative solder work I botched a few things up. But it's almost imperceptible if you squint)
However, I did manage to read the video stream, convert it from YUV to RGB and scale it to the native resolution of the PSP screen. I even had a little bandwidth left for a small overlay window (see below)
I wanted to find out what I could do with a video stream on my DE0-Nano. Process it? Maybe warp it and feed it into my Oculus Rift via HDMI ?
Turns out, FPGAs are awesome but the DE0-Nano is equipped with a relatively slow RAM that becomes a bottleneck when it comes to video processing which requires huge amounts of memory bandwidth. It was just not intended to be a video powerhouse.
For now a short summary.
The idea was to play around with analog video as I came across this nifty chip from TI (TVP5150). It does all the heavy lifting when it comes to dealing with the analog signals and outputs a convenient stream of digital data for you (although in a somewhat inconvenient format called BT.656).
What is this?
I found this project in a drawer and thought I'd post it before it disappears forever.
This page is a little sparse, so while I'll be digging out a few more details over time I'll add more info as it comes up (or somebody asks me about it).
As a test video source I used an old DVD player and an even older movie.
Apart from that I used a few more of Altera's IP cores to chain together a small video pipeline.
Clocked video in and outputs, color and format conversion, deinterlacing, scaling, frame buffers and fifos. I'll post a graphic once I've reinstalled Quartus.
Edit: I added a flowchart to the bottom of the page. Scroll down..
The brunt of the work is happening inside the FPGA. The TVP5150 has about 1 million configuration registers that have to be accessed over I2C. So the good old NiosII core came in handy to do this housekeeping and a few other debugging tasks.
Altera's Video and Image Processing Suite is full of goodies.
Apart from all the things I created in this NiosII with SDRAM and this PSP Screen tutorial, I added the following:
What's interesting is how the data comes in and flows through various conversion steps and clock domains. The TVP5150 delivers the data as 16 bit YUV 4:2:2, 8 bit at a time at 27 Mhz. The Color Plane Sequencerreshuffles this into a single symbol 16 bit wide that can be transported over the bus in one cycle/beat.
After selecting a convenient crop of the image and scaling it to a square pixel aspect ratio (looking at fields, ignoring deinterlacing) the pixels are then stored in the Frame Buffer, still in the 4:2:2 format since this is less data to store.
The Chroma Resampler then restores the full color resolution (4:4:4) and the pixels are finally converted to RGB which can be fed to the PSP screen.
The rest of the cores are reading an image buffer from sdram and composite it over the video stream.
happy gate clobbering.
Links:
Video and Image Processing Suite
Other projects you might like
