The following scenarios use an assembly language Delay Slot for either accuracy or performance.
The MIPS processor uses an "5 stage instruction pipeline". Each stage can be completed independently and passes it result to the next stage.
Some instructions either can't complete their task or will use a data value that isn't ready which breaks each instruction into 5 phases (VR4300i).
So the CPU has 5 different sections that each work on their phase independently.
Some instructions can cause the pipeline to "stall" or wait for a result, this includes lw (Load Word) a 1 Instruction delay and the *MULT* and *DIV* instructions 2-8 instruction delay. As an assembly language programmer, plan ahead and try to keep the CPU busy.