Stepper motor

Theory:Stepper motors are designed as an open loop system. A pulse generator sends out pulses to the phase sequencing circuit 

Diagram:

Verilog code:

module Stepper (input clk, input din, output angle);

  wire clk_1;

  reg [26:0] clk_div;

  always @(posedge clk)

    begin

      clk_div <= clk_div + 1;

    end

  assign clk_1 = clk_div[18];

  always @(posedge clk)

    begin

      if (din == 1)

        begin

          angle <= {1'b0, 1'b1, 1'b0, 1'b1};

        end

      else

        begin

          angle <= {1'b1, 1'b0, 1'b1, 1'b0};

        end

    end

endmodule

Output:

Device utilization: