Theory:a finite-state machine whose current output values are determined only by its current state. This is in contrast to a Mealy machine, whose output values are determined both by its current state and by the values of its inputs.
Circuit diagram:
Truth table:
verilog code:
module Bcd_to_excess3_mosel(
input clk,
input reset,
input [3:0] BCD,
output reg [3:0] Cexcess
);
reg [2:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @(posedge clk) begin
if (reset)
state <= S0;
else
state <= next_state;
end
always @(*) begin
case (state)
S0: next_state = S1;
S1: next_state = S2;
S2: next_state = S3;
S3: next_state = S0;
default: next_state = S0;
endcase
end
always @ (state) begin
case (state)
s0: excess 3 = BCD + 4'booll;
s1: excess 3 = BCD + 4'booll;
s2: excess 3 = BCD + 4'booll;
s3: excess 3 = BCD + 4'booll;
default: excess 3 = 4'b0000;
endcase
end
end module
Test bench code:
`timescale 1ns / 1ps
module tb_Bcd_to_excess3_mosel;
reg clk;
reg reset;
reg [3:0] BCD;
wire [3:0] Cexcess;
Bcd_to_excess3_mosel uut (
.clk(clk),
.reset(reset),
.BCD(BCD),
.Cexcess(Cexcess)
);
// Clock generation: 10ns period
always #5 clk = ~clk;
initial begin
$display("Time\tBCD\tCexcess");
$monitor("%0dns\t%b\t%b", $time, BCD, Cexcess);
// Initialize signals
clk = 0;
reset = 1;
BCD = 4'd0;
// Reset pulse
#10 reset = 0;
// Apply input values
#10 BCD = 4'd0;
#10 BCD = 4'd1;
#10 BCD = 4'd5;
#10 BCD = 4'd9;
#10 BCD = 4'd4;
// Finish
#20 $finish;
end
endmodule
Pin assigment:
PIN_A1 -to clk
PIN_B1 -to reset
PIN_C1 -to BCD[0]
PIN_C2 -to BCD[1]
PIN_C3 -to BCD[2]
PIN_C4 -to BCD[3]
PIN_D1 -to Cexcess[0]
PIN_D2 -to Cexcess[1]
PIN_D3 -to Cexcess[2]
PIN_D4 -to Cexcess[3]
RTL schematic view:
output:
Device utilization :
Time analysis: