Objective:

To design and implement a digital stopwatch system using seven-segment display that counts from 0 to 9, with control functionalities including Start/Stop and Reset buttons. The aim is to understand the principles of sequential circuit design, state machine implementation, timing control, and hardware interfacing in a digital system.

Introduction:

A stopwatch is a simple yet essential digital timing device used to measure elapsed time. In this experiment, we design a basic stopwatch that displays digits from 0 to 9 using a seven-segment display. The system includes two control buttons: Start/Stop to control the counting operation and reset to return the count to zero. This project demonstrates fundamental concepts of digital system design such as counter implementation, button debouncing, and display interfacing.

Methodology:  

 1. Design a Mod-10 Counter using flip-flops or behavioural modelling to count from 0 to 9.

 2. Interface a Seven-Segment Display to show the current count using a decoder.

 3. Implement Start/Stop Control using a button to enable or disable the counter clock.

 4. Implement Reset Functionality to asynchronously or synchronously reset the count to zero.

 5. Simulate and verify the design using a hardware description language like Verilog.

 6. Download the design to FPGA (if applicable) for hardware validation.

CODE:

`timescale 1ns / 1ps

module stop4(

input clk,           

input start_stop_btn,

input reset_btn,     

output reg [6:0] seg,

output reg en1,      

output reg en2       

);

reg [23:0] clkdiv = 0;

reg one_sec_tick = 0;

always @(posedge clk) begin

     if (clkdiv == 24'd12_499_999) begin 

         clkdiv <= 0;

         one_sec_tick <= 1;

     end else begin

         clkdiv <= clkdiv + 1;

         one_sec_tick <= 0;

     end

end

 reg [1:0] start_sync = 0;

reg [1:0] reset_sync = 0;

 always @(posedge clk) begin

     start_sync <= {start_sync[0], start_stop_btn};

     reset_sync <= {reset_sync[0], reset_btn};

end

wire start_rising = (start_sync == 2'b01);

wire reset_rising = (reset_sync == 2'b01);

reg running = 0;

reg [3:0] count1 = 0;

reg [3:0] count2 = 0;

always @(posedge clk) begin

     if (start_rising)

         running <= ~running;

  if (reset_rising) begin

         count1 <= 0;

         count2 <= 0;

         running <= 0;

     end else if (one_sec_tick && running) begin

         if (count1 == 9) begin

             count1 <= 0;

             if (count2 == 5) // stop at 59 and reset to 0

                 count2 <= 0;

             else

                 count2 <= count2 + 1;

         end else

             count1 <= count1 + 1;

     end

end

reg [15:0] mux_clkdiv = 0;

reg display_toggle = 0;

always @(posedge clk) begin

     if (mux_clkdiv == 49999) begin

         mux_clkdiv <= 0;

         display_toggle <= ~display_toggle;

     end else

         mux_clkdiv <= mux_clkdiv + 1;

end

function [6:0] seg7;

     input [3:0] val;

     begin

         case (val)

             4'd0: seg7 = 7'b0111111;

             4'd1: seg7 = 7'b0000110;

             4'd2: seg7 = 7'b1011011;

             4'd3: seg7 = 7'b1001111;

             4'd4: seg7 = 7'b1100110;

             4'd5: seg7 = 7'b1101101;

             4'd6: seg7 = 7'b1111101;

             4'd7: seg7 = 7'b0000111;

             4'd8: seg7 = 7'b1111111;

             4'd9: seg7 = 7'b1101111;

             default: seg7 = 7'b0000000;

         endcase

     end

endfunction

always @(posedge clk) begin

     if (display_toggle) begin

         en1 <= 1;   

         en2 <= 0;   

         seg <= seg7(count2);

     end else begin

         en1 <= 0;   

         en2 <= 1;   

         seg <= seg7(count1);

     end

end

endmodule

Verilog Testbench:

module stp1_tb;

       // Inputs

       reg clk;

       reg start_stop_btn;

       reg reset_btn;

       // Outputs

       wire [6:0] seg;

       wire en;

       // Instantiate the Unit Under Test (UUT)

       stopwatch uut (

                 .clk(clk),

                 .start_stop_btn(start_stop_btn),

                 .reset_btn(reset_btn),

                 .seg(seg),

                 .en(en)

       );

       initial begin

                 // Initialize Inputs

                 clk = 1; reset_btn = 1; #100;

       start_stop_btn = 1;

                 // Wait 100 ns for global reset to finish

                 #100;

     end

                   initial begin

                   forever #50 clk =~clk;

                 end

endmodule

UCF FILE:

NET "seg[7]" LOC = P19;

NET "seg [6]" LOC = P18;

NET "seg[5]" LOC = P16;

NET "seg[4]" LOC = P15;

NET "seg[3]" LOC = P13;

NET "seg[2]" LOC = P12;

NET "seg[1]" LOC = P11;

NET "seg[0]" LOC = P10;

NET "en[1]" LOC = P166;

NET "en[2]" LOC = P167;

NET "reset_btn" LOC = P133;

NET "start_stop_btn" LOC = P21;

NET "clk[1]" LOC = P79;