Full adder structural description

Theory:A full adder is a combinational logic circuit that forms the arithmetic sum of three bits.

it consists of three inputs and two outputs. which performs the addition of three bits A ,B and Cin and it produces sum & carry as Outputs.

BOOLEAN EXPRESSION:

SUM = A ^ B ^ C

CARRY = (A & B) | (B & C) | (A & C)

Verilog code:

module full_adder( S, Cout , a, b, cin); 

input a, b, cin;

output S, Cout;

wire w1,w2,w3,w4;

xor g1(w1,a,b);

xor(sum,w1,cin);

and g3(w2,a,b);

and g4(w3,Cin,b);

and g5(w4,Cin,a);

or g6(w4,Cin,a);

end module

Testbench code:

module Tb_g; reg a,b,c; wire sout,cout;

FA_gate FA(a,b,c,sout,cout);

initial begin a=1'b0; b=1'b0; c=1'b0; #10;

a=1'b0; b=1'b0; c=1'b1; #10;

a=1'b0; b=1'b1; c=1'b0; #10;

a=1'b0; b=1'b1; c=1'b1; #10;

a=1'b1; b=1'b0; c=1'b0; #10;

a=1'b1; b=1'b0; c=1'b1; #10;

a=1'b1; b=1'b1; c=1'b0; #10;

a=1'b1; b=1'b01; c=1'b1; #10;

$finish;

 end endmodule

Pin assignment;

  input a->pin 86

       input b->pin 90 

        input Cin->pin 94

        output sum->pin 20

        output carry->pin 26