Theory:

AOI (AND-OR-Invert) logic is a fundamental logic gate structure widely used in digital electronics, particularly in VLSI design. It is a combinational logic configuration where inputs are first processed by AND gates, then combined using OR gates, and finally the output is inverted (NOT operation). 

Boolean expression:

Y=∼((A⋅B)+C) 

Verilog code:

module AOI22 (

    input reg A, B, C, D,

    output reg Y

);

always @ (A or B or C or D) begin

    Y = ~((A & B) | (C & D));

end

endmodule

   TESTBENCH CODE:

module tb_AOI22;

  // Declare testbench variables

  reg A, B, C, D;

  wire Y;

  // Instantiate the AOI22 module

  AOI22 uut (

    .A(A), .B(B), .C(C), .D(D),

    .Y(Y)

  );

  // Test sequence

  initial begin

    $display("A B C D | Y");

    $monitor("%b %b %b %b | %b", A, B, C, D, Y);

    // Apply test vectors

    A = 0; B = 0; C = 0; D = 0; #10;

    A = 0; B = 1; C = 0; D = 1; #10;

    A = 1; B = 1; C = 0; D = 0; #10;

    A = 0; B = 0; C = 1; D = 1; #10;

    A = 1; B = 1; C = 1; D = 1; #10;

    A = 1; B = 0; C = 1; D = 0; #10;

    $finish;

  end

endmodule

Output:

Pin Assignment:  

RTL Schematic view:  

Device utilization summary:

Timing analysis: