Mealy

Theory:The Mealy machine associates an output value with each transition edge, this output value is determined both by its current state and the input of the transition edge 

Circuit diagram

Truth table:

Verilog code:

module BCC_to_excess_3b (Bout, Bin, clk, reset_b);

output B_out;

input Bin, clk, reset_b;

parameter s_0 = 3'b000;

s_1 = 3'b001;

s_2 = 3'b010;

s_3 = 3'b011;

s_4 = 3'b100;

s_5 = 3'b101;

s_6 = 3'b110;

dont_case_state = 3'bxx;

dont_case_out = 1'bx;

reg [2:0] state, next_state;

reg B_out;

always @ (posedge clk or negedge reset_b)

if (reset_b == 0) state <= s_0; else state <= next_state;

always @ (state or Bin) begin

B_out = 0;

case (state)

s_0: if (Bin == 0) begin next_state = s_1;

B_out = 1;

else if (Bin == 1) begin next_state = s_2; end

s_1: if (Bin == 1) begin next_state = s_3; B_out = 0; end

s_2: begin next_state = s_4; B_out = Bin; end

default: next_state = s_0;

endcase

end

endmodule

Test bench code:

`timescale 1ns/1ps

module test_BCC_to_excess_3b;

    reg Bin, clk, reset_b;

    wire B_out;

    // Instantiate the module

    BCC_to_excess_3b uut (

        .B_out(B_out),

        .Bin(Bin),

        .clk(clk),

        .reset_b(reset_b)

    );

    // Clock generator

    always #5 clk = ~clk;

    // Stimulus

    initial begin

        $display("Time\tclk\treset_b\tBin\tB_out");

        $monitor("%0t\t%b\t%b\t%b\t%b", $time, clk, reset_b, Bin, B_out);

        // Initialization

        clk = 0;

        reset_b = 0;

        Bin = 0;

        // Reset the system

        #10 reset_b = 1;

        // Apply test input sequence

        #10 Bin = 0;

        #10 Bin = 1;

        #10 Bin = 1;

        #10 Bin = 0;

        #10 Bin = 1;

        #10 Bin = 1;

        #10 Bin = 0;

        #20 $finish;

    end

endmodule

Pin assignment:

         input a->pin 86

       input b->pin 90 

        input Cin->pin 94

        output sum->pin 20

        output carry->pin 26

output:

RTL schematic vew:

Device utilization table:

Time analysis: