Theory:
The RCA (Ripple Carry Adder) is a basic and widely used adder circuit in digital electronics, especially for adding two binary numbers. The Ripple Carry Adder works by adding the corresponding bits from the two numbers one at a time, starting from the least significant bit (LSB) to the most significant bit (MSB). The carry from each bit addition "ripples" through to the next bit.
Circuit diagram:
Verilog code:
module ripple_carry_adder (
input [1:0] A, B, // 2-bit inputs A and B
input Cin, // Carry-in
output [1:0] Sum, // 2-bit Sum output
output Cout // Carry-out
);
// Intermediate carry signal for the first bit
wire C1;
// Sum and carry calculations using dataflow
assign Sum[0] = A[0] ^ B[0] ^ Cin; // Sum for the LSB (S0)
assign C1 = (A[0] & B[0]) | (Cin & (A[0] ^ B[0])); // Carry for the LSB (C1)
assign Sum[1] = A[1] ^ B[1] ^ C1; // Sum for the MSB (S1)
assign Cout = (A[1] & B[1]) | (C1 & (A[1] ^ B[1])); // Carry-out for MSB (Cout)
endmodule
TESTBENCH CODE:
module test_ripple_carry_adder;
// Declare the input and output variables for the RCA module
reg [1:0] A, B; // 2-bit input A and B
reg Cin; // Carry-in input
wire [1:0] Sum; // 2-bit Sum output
wire Cout; // Carry-out output
// Instantiate the ripple_carry_adder module
ripple_carry_adder RCA (
.A(A),
.B(B),
.Cin(Cin),
.Sum(Sum),
.Cout(Cout)
);
initial begin
// Display the header for the truth table
$display("A B Cin | Sum Cout");
$display("-----------------------");
// Test Case 1: A = 00, B = 00, Cin = 0
A = 2'b00; B = 2'b00; Cin = 0;
#10; // Wait for 10 time units
$display("%b %b %b | %b %b", A, B, Cin, Sum, Cout);
// Test Case 2: A = 01, B = 01, Cin = 0
A = 2'b01; B = 2'b01; Cin = 0;
#10;
$display("%b %b %b | %b %b", A, B, Cin, Sum, Cout);
// Test Case 3: A = 10, B = 01, Cin = 0
A = 2'b10; B = 2'b01; Cin = 0;
#10;
$display("%b %b %b | %b %b", A, B, Cin, Sum, Cout);
// Test Case 4: A = 11, B = 01, Cin = 0
A = 2'b11; B = 2'b01; Cin = 0;
#10;
$display("%b %b %b | %b %b", A, B, Cin, Sum, Cout);
// Test Case 5: A = 01, B = 01, Cin = 1
A = 2'b01; B = 2'b01; Cin = 1;
#10;
$display("%b %b %b | %b %b", A, B, Cin, Sum, Cout);
// Test Case 6: A = 10, B = 10, Cin = 1
A = 2'b10; B = 2'b10; Cin = 1;
#10;
$display("%b %b %b | %b %b", A, B, Cin, Sum, Cout);
// Test Case 7: A = 11, B = 11, Cin = 0
A = 2'b11; B = 2'b11; Cin = 0;
#10;
$display("%b %b %b | %b %b", A, B, Cin, Sum, Cout);
// Test Case 8: A = 11, B = 11, Cin = 1
A = 2'b11; B = 2'b11; Cin = 1;
#10;
$display("%b %b %b | %b %b", A, B, Cin, Sum, Cout);
$finish; // End the simulation
end
endmodule
Output:
Device utilization:
RTL schematic view:
Time analysis: