Verilog_programming

Assigning values in Verilog: difference between assign, <= and =

1. "<=" non-blocking is performed on every positive edge of the clock. These are evaluated in parallel so no guarantee of order. An example of this would be a register.

2. "assign =" continual assignment to wire outside an always statement. The value of LHS is updated when RHS changes.

3. "=" blocking assignment, inside always statements enforces sequential order.

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EDA Playground

How to Write a Basic Verilog Testbench

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Verilog HDL: Creating a Hierarchical Design

Testbench 介紹

design.sv

// Design

// D flip-flop

module dff (clk, reset,

  d, q, qb);

  input      clk;

  input      reset;

  input      d;

  output     q;

  output     qb;

  reg        q;

  assign qb = ~q;

  always @(posedge clk or posedge reset)

  begin

    if (reset) begin

      // Asynchronous reset when reset goes high

      q <= 1'b0;

    end else begin

      // Assign D to Q on positive clock edge

      q <= d;

    end

  end

testbench.sv

// Testbench

module test;

  reg clk;

  reg reset;

  reg d;

  wire q;

  wire qb;

  // Instantiate design under test

  dff DFF(.clk(clk), .reset(reset),

          .d(d), .q(q), .qb(qb));

  initial begin

    // Dump waves

    $dumpfile("dump.vcd");

    $dumpvars(1);

    $display("Reset flop.");

    clk = 0;

    reset = 1;

    d = 1'bx;

    display;

    $display("Release reset.");

    d = 1;

    reset = 0;

    display;

    $display("Toggle clk.");

    clk = 1;

    display;

  end

  task display;

    #1 $display("d:%0h, q:%0h, qb:%0h",

      d, q, qb);

  endtask

endmodule

run.do

setup_design -manufacturer Xilinx -family Artix-7 -part 7A100TCSG324

foreach arg $::argv {

  add_input_file $arg

}

compile

synthesize

auto_write precision.v

report_output_file_list

report_area

report_timing

exec cat precision.v