Overview of Status of Analysis, Design, Fabrication, Tests, etc.
PCB came in on Wednesday
Plan C bracket complete and ready for testing (Sponsor to wire bond at SPAWAR)
All parts were machiened as of 5-29
Test to be done next Tuesday due to chip selection.
Testing for temperature and electrical signal at 4K
2nd draft of report turned in and comments made on team 20 report
2nd draft of website turned in
Accomplishments from Previous Week
Set up time to visit OASIS on Thursday to discuss final design with engineering
Created interface layer for layered design
Milled holes into PCB for layered design
Set time to test plan C bracket at SPAWAR.
Electrical and temperatrue test to be ran concurrently
Goals for Next Week (list names after each item). Use specific and measurable objectives.
Test Plan C bracket at SPAWAR (group)
Sponsor to wire bond to traces for testing of electrical connection
Meet with OASIS Engineering to talk about ideal design and finalize it (whoever can make it)
Work on Poster for finals week (group)
Work on Report and website (group)
Organize referance data and use in report where necessary to show more information on material selection (Patrick)
Sponsor Comments from Last Meeting and Actions Taken to Address these Comments (indicate date of comments and if via email or in person)
Several suggestions were made to improve the current design for better thermal and electrical connections (In Person, 5/29)
Indium layers to prop up the chip across from the electrical bumping. This will prevent the chip resting at an angle and leaving space between the holding bracket and the chip.
Indium bumping instead of gold bumping (indium is softer, used in cryogenic temperatures)
Three different types of models should be made (ideal solution):
Return to Fuzz Buttons (leave empty vias to place fuzz buttons in)
Ideal Solution
Beryllium Copper "fingers" for better electrical connections (similar to fuzz buttons)
Electrical traces should not make 90 degree turns as in current design. Ideally each trace would be a straight line (In Person, 5/29)
A meeting has been set up between a RF chip testing expert and ourselves to provide input on the ideal solution (In Person, 5/29)
Instructor Comments from Last Meeting and Actions Taken to Address these Comments (indicate date of comments and if via email or in person)
Instructor suggested using a modified wire-bonding process (the deposit without the wire) for our prototype testing. (In Person, 5/21)
Ideal solution should be finalized for sponsor ASAP (In Person, 5/21)
Comments from Other Students in the Class (indicate date of comments and if via email or in person)
Risks and Areas of Concern
Testing of prototype:
Will the prototype get down to 4K. This will be tested at the sponsor's lab, but given the use of many not-so-good thermal conductors this may be a problem.
Electrical connection between chip pads and electrical interface layer.
Resources or Information Required but not Available
Schedule
Finalize design with Oasis Materials and have everything in place for sponsor.
We plan to visit Sorin from Oasis on May 31, 2012
Update Gantt chart.
Budget (list amount spent and amount remaining)
Progress on Report and Webpage