Even.Semester.2015.PS864.Embedded Controller Design Lab

Post date: Oct 31, 2014 7:06:09 AM

• PS864 Announcements:

Date: Oct. 31, 2014

1. PS864 Elective will be offered to PG students of EE Dept.for session EVEN Semester, 2015 as per course & evaluation plan listed in pdf file: EVEN.2015.PS864.ECDLAB.CnEPLAN.KPV.pdf.

2. All registrants are required to confirm their registration during pre-registration process to enable resource planning.

3. Please find relevant course documents posted under course EE335, in separate link.

Date: 06/01/2015

1. PS864 Lab commences from 12th Jan, 2015 as introductory session.

2. Roll numbers falling in various Groups, Day and time slot for the groups is as following:

• MON, 2-3.30PM GROUP 1: 4 Research Scholars + 14PS01 - 14PS12

• MON, 3.30-5PM GROUP 2: 14PS13 - 14PS26

Date: 09/04/2015

1. Please find mini project marks of all registrants in EVEN.2015.PS864.ECDLAB.MINIPROJ.MARKS.pdf.

2. PS864 END-SEM EXAM Time Table and Conduction procedure:

The day and time slot for the Lab End-Semester Exam is as follows:

3. First registrant will be seated on the front bench at L-303, then enters roll number in answer book issued to him. Question slip will be randomly picked by registrant and copies question in to the answer book, then returns slip. Slip given should be returned without any marking on it. Following this, registrant completes his/her design write up in an answer book (supplied by the dept.) during first 30 minutes, and proceeds to work table at #204, Microprocessor Lab for implementation on his / her lap top or Desk Top Computer.

4. Majority of questions are framed and targeted to realise using state diagram only (with few exception using MSI Building blocks). Write up in an answer book shall be presented up to tight state diagram with state assignment (few cases MSI building blocks) only. This write up shall be submitted after first 30 minutes. Following this, registrant will transfer state diagram / building blocks in work sheet and proceeds to work table to implement simulation.

5. Finally registrant is required to demonstrate Timing simulation outputs for the Problem statement during last 30 minutes. It is desired that, the simulation should be ready 30 minutes before the session closing time.

6. Evaluation metrics of End Sem Examination:

1. Write up: 15 marks,

2. Timing Simulation on Xilinx ISE Platform in VERILOG (Schematic entry only if problem specifies): 25 marks.

Date: 15/04/2015

1. Please find overall distribution of marks under various components of all PS864 Registrants in a file: EVEN.2015.PS864.ECDLAB.MARKS.pdf.

Date: 12/05/2015

1. Please find semester performance marks and grades of all registrants in EVEN.2015.PS864.2PS.KPV.PDF (Submitted for DPGC Approval).

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