Even.Semester.2018.EE335.Digital System Design Lab

Post date: Dec 31, 2013 1:35:36 PM

• EE335 Announcements:

Important note for Auditing the course:

1. Registrants are required to meet course instructor and get entry of Audit registry in IRIS to complete registration procedure.

2. Auditing registrants are required to comply with minimum class attendance requirements as per academic regulations.

3. Auditing registrants are required to undergo Course evaluation of all In-semester components, namely Tutorial, Mini project and Mid - Semester exam. Total marks obtained out of all these components shall not fall below 20, to award 'U' grade.

Important note for Dropping or Auditing the course:

1. Please send email to "vittal@nitk.edu.in" specifying following: Name, Roll number (15EEXXX), Course name, Course code, Dropping or Auditing

• All Teaching Assistants, Research scholars and PG students associated with lab are required follow the guidelines listed in EE335DSDLAB_TA_GUIDELINES.pdf

Date: Nov. 07, 2017

1.EE335 Elective will be offered to 6th Semester B.Tech.(EE) students for session EVEN Semester, 2018 as per course & evaluation plan listed in pdf file: EVEN.2017.EE335.DSDLAB.CnEPLAN.KPV.pdf

2.All registrants are required to confirm their registration during pre-registration process to enable resource planning.

3.Please follow videos posted through YouTube by Xilinx, Digilent, NPTEL, EDA playground, AllAboutEE, CellRider, latestnews as supplementary self learning material. Find such links posted in my website under "Useful link" menu.

Date: Dec, 26, 2017

1.All registrants are suggested to go through the following pdf files listed herewith and follow the steps in c. ... Tutorial.pdf during introductory LAB session week "4-8, JAN,16":

(a.) XILINX_TOOL_FLOW_PPT.pdf, (b.) Xilnx ISE webpack Introduction.pdf, (c.) Xilinx ISE WebPACK Schematic Capture Tutorial.pdf (Simulate using ISE and input using Test bench waveform tool), (d.) ISE.XILINX.TUTORIAL8.2i.pdf

2. Group allocation will be announced on Jan, 01, 2018 and lab will commence on Jan, 03, 2018.

Date: 01/01/2018

1. EE335 Lab commences from 03rd Jan, 2018 as an introductory session.

2. Roll numbers falling in various Groups, Day and time slot for the groups is as following:

• • WED, 2 - 5 PM GROUP 1: 15EE101 - 15EE128

  • WED, 2 - 5 PM GROUP 2: 15EE130 - 15EE151

  • THU, 2 - 5 PM GROUP 3: 15EE154 - 14EE232

  • THU, 2 - 5 PM GROUP 4: 15EE233 - 15EE254

3. All registrants have to bring their laptop computer (optional) to the lab every session. Xilinx ISE Software will be supplied in USB memory stick through CR.

4. All course registrants are requested to sign in as a user in www.xilinx.com. Obtain license file online for ISE tools installed in respective laptops. (MAC id, or Hard disk id will be used).

5. Read through ISE Tutorials: Xilinx ISE WebPACK Schematic Capture Tutorial.pdf (Simulate using ISE and input using Test bench waveform tool) supplied below in pdf.

Date: 10/01/18

Session - 1

1. Please find lab session 1 exercises listed in pdf file attachment: DSD-LAB-MANUAL.pdf.

2. All students are required come with design work out of the exercises in long note book, and at lab ISE software will be used for schematic entry and simulation study.

Date: 17/01/18

Session - 2

1. Please find lab session 2 exercises listed in pdf file attachment: DSD-LAB-MANUAL.pdf..

2. Refer to Xilinx_Schematic_Entry_Tutorial.pdf to guide through the exercise. Complete assignment to get lab performance marks.

Date: 24/01/18

Session - 3

1. Please find lab session 3 exercises listed in pdf file attachment DSD-LAB-MANUAL.pdf..

2. Refer to ISE_XILINX_TUTORIAL8.2i.pdf

Date: 31/01/18

Session - 4

1. Please find lab session 4 exercises listed in pdf file attachment DSD-LAB-MANUAL.pdf.

2. Get familiar with various building blocks required for simple digital system, eg. Binary-XS3 code converter.

3. In order to enhance learning, please find additional synthesizable verilog codes for digital building blocks in following file: Verilog examples.rar

Date: 15/02/2018

Mid semester revision Session

1. It is revision and wrap up session of all previous lab sessions. All incomplete lab modules have to completed.

2. Group 1 & 2 will attend the lab on 15/2/18 between 2 pm-3.30 pm and Group 3 & 4 will attend the lab between 3.30 pm - 5.00 pm.

Date: 21/02/2018

Mid Sem Lab Exam

1. Please solve the Test question announced at the lab by building hierarchical design using VERILOG.

2. Complete up to timing simulation and get evaluated.

3. Mid sem evaluation is for 20 marks (X). It will be averaged with session marks average (Y). Wherein net lab session average Z = (X + Y)/2

4. Coming weeks we will have exercise on BASYS 2/3 FPGA kit. Two per group will do experiments. Two batches having lab same day will attend lab from 2pm - 5pm.

MINI PROJECT ALLOCATION PROCESS:

1. Mini projects shall be assigned to all registrants out of 30 projects listed in the pdf file by random pick of slip in the classroom CR5, LHC-C, NITK on 21/02/18, 11.05AM - 12.00NOON.

2. Mini projects are drawn from various textbooks specified by id: T1, T2.... On allocation of the project, registrant under course EE311 will be submitting a Mini project report in a . Sessional book (available in Student co.ops) as per date specified in calendar.

3. Registrant under EE335 will be implementing the project on Xilinx ISE platform and up to timing simulation.

4. Please find respective mini project statements in respective pdf files marked as T1, T2.... under course announcement section of EE311...

Note: All BASYS 2/3 Board experiments are done with Two per group. Two batches having lab same day will attend lab from 2pm - 5pm.

Date: 07/03/18

Session - 5

1. Please find lab session 5 exercises listed in pdf file attachment DSD-LAB-MANUAL.pdf.

2. Please download and install Adept software (complete system) on your computer, directly from Digilent website.

3. Refer to Adept software basic tutorial.pdf, XILINX ISE webpack schematic capture tutorial.pdf

4. Please take care of Basys 2/3 board by handling gently to avoid physical damage and do not touch components to prevent damage due to ESD.

5. Use EE335.txt or EE335.doc only as UCF file for mapping I/O resource on Basys 2/3 board.

6. In order to enhance learning, please realise your choice of machine interface on BASYS 2/3 Board, but never violate UCF to care for FPGA I/O pins.

Date: 14/03/18

Session - 6

1.Please find lab session 6 exercises listed in pdf file attachment DSD-LAB-MANUAL.pdf.

2. Take care of dividing clock and synchronising control inputs with clock, to facilitate coordination.

3. Repeat the above exercises and realise sequential machine for code conversion. Use schematic design if found convenient. Transfer sliding switch input to a shift register and then perform SO to feed sequential code converter. Use register buffered I/O to use I/O resources.

4. Design a 4-bit ring counter and display binary output on 7-segment display as a rolling display. (0001-0010-...).

5. In order to enhance learning, please realise your choice of machine interface on BASYS 2/3 Board, but never violate UCF to care for FPGA I/O pins.

Date: 21/03/2018

Session - 7

End semester revision Session

1. It is revision and wrap up session of all previous lab sessions. All incomplete lab modules have to completed. Sessions that follow next week will be mini project session.

2. Those who were absent due to institute approved extra curricular activities (viz. NCC, NSS, Sports) missing lab session experiments will be evaluated in this session. (only on submission of official participation document from the institute). For others it is essentially a wrap up session.

3. Please refer to Class Calendar (link) for noting time line of events (select agenda format).

4. In order to enhance learning, please realise your choice of machine interface on BASYS 2/3 Board, but never violate UCF to care for FPGA I/O pins.

Date: 23/03/18

1. Please find DSD Lab Total Average marks of (all sessions Plus mid semester exam) in a file EVEN.2018.EE335.DSDLAB.MIDSEM.MARKS.PDF along with attendance position.

2. Please find attendance status up to mid sem exam in EVEN.2018.EE335.DSDLAB.MIDSEM.ATTENDENCE.PDF. In case attendance is below 75%, you are required to meet Course Instructor, FA and HOD.

MINI PROJECT ANNOUNCEMENTS

1. Please find Mini project allocation list in pdf file: EVEN.2018.EE335.MINI.PROJECT.ALLOCATION.pdf

2. Please find Mini project evaluation metrics listed in pdf file: EE335.MINIPROJ.EVAL.METRICS.pdf

3. The hardware realization of Mini project on BASYS 2/3 Board will not be permitted due to resource constraints. The timing simulation of project work shall be presented with complete clarity.

4. The Mini project evaluation:

• Mini Project Submissions:

  • Date of submission: 04/04/2018, 5pm

  • Submission of EE335 Min project in CD (whole class in single CD) with a folder named as per registered number format as: YYEEXX / YYPSXX.

• Lab mini project evaluation:

  • During regular Lab schedule hours from 04/04/2018 - 05/04/2018 with 15 minutes demo time per registrant with 3 student in one time slot, in the order of registration number (lab time will extend beyond lab hour up to night, till completion of that days batch.) The registrant can arrive just one slot before his turn to the lab)

Date: 28/03/2018

Session - 8

1. This week it is session for Mini Project work.

2. At lab you are required to work towards completion of Mini Project allocated to you.

Date: 28/03/2018

Session - 9

1. This is second week for working on Mini Project.

2. At lab you are required to work towards completion of Mini Project allocated to you.

Date: 04/03/2018

1. Mini project evaluation will be carried out this week.

2. During regular Lab schedule hours from 04/04/2018 - 05/04/2018 with 15 minutes demo time per registrant with 3 student in one time slot, in the order of registration number. The registrant can arrive just one slot before his turn to the lab)

Date: 09/04/2018

1. Please find lab in sem marks of all registrants in EVEN.2018.EE335.INSEM.MARKS.pdf.

2. Please find attendance status up to end sem exam in EVEN.2018.EE335.SEM.ATTENDANCE.PDF. In case attendance is below 75%, you are required to meet Course Instructor, FA and HOD.

EE335 LAB END-SEM EXAM Time Table:

The day and time slot for the Lab End-Semester Exam is as follows:

3. First registrant will be seated on the front bench at L-303, then enters roll number in answer book issued to him. Question slip will be randomly picked by registrant and copies question in to the answer book, then returns slip. Slip given should be returned without any marking on it. Following this, registrant completes his/her design write up in an answer book (supplied by the dept.) during first 30 minutes, and proceeds to computer work table at #206, Computer Lab for implementation on his / her lap top (most preferable). Only in case of emergency Desk Top Computer will be given.

4. Majority of questions are framed and targeted to realise using state diagram only (with few exception using MSI Building blocks). Write up in an answer book shall be presented up to tight state diagram with state assignment (few cases MSI building blocks) only. This write up shall be submitted after first 30 minutes. Following this, registrant will transfer state diagram / building blocks in work sheet and proceeds to work table to implement simulation.

5. Finally registrant is required to demonstrate Timing simulation outputs for the Problem statement during last 30 minutes. It is desired that, the simulation should be ready 30 minutes before the session closing time.

6. Evaluation metrics of End Sem Examination:

1. Write up: 15 marks,

2. Timing Simulation on Xilinx ISE Platform in VERILOG: 25 marks.

Date: 18/04/2018

1. Please find semester performance marks of all registrants in EVEN.2018.EE335.TOTAL.MARKS.pdf and total attendance status in EVEN.2018.EE335.ATTENDANCE.PDF.

Date: 08/05/2018

1. Please find semester performance marks and grades of all registrants (DUGC Approved) in EVEN.2018.EE335.6EE.KPV.PDF.

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