🧲 Unified Polarization Framework: Represents total polarization as the combination of irreversible switching, intrinsic dielectric response, and reversible domain-wall motion.
📈 Large-Signal P–V Modeling: Uses distributed domain switching kinetics to reproduce hysteresis, coercive-voltage distribution, partial switching, and frequency-dependent polarization loops.
📊 Small-Signal C–V Modeling: Predicts branch-dependent butterfly-shaped capacitance using reversible domain-wall response around the instantaneous polarization state.
🧱 Multidomain Representation: Models the ferroelectric as an ensemble of domains with distributed switching barriers, switching times, and local interactions.
⏱️ Frequency-Dependent Response: Includes separate dynamic time scales for fast intrinsic dielectric polarization and slower domain-wall motion.
🔄 Arbitrary Waveform Support: Evolves the same internal states under triangular sweeps, sinusoidal excitation, pulses, minor loops, and mixed-amplitude waveforms.
💻 Circuit-Compatible Implementation: Formulated using terminal charge and internal state variables for implementation in Verilog-A and SPICE-compatible simulators.
Developed a single framework that captures both irreversible switching and reversible dielectric response.
Linked irreversible polarization to multidomain switching and reversible capacitance to domain-wall availability.
Included frequency dependence, minor loops, partial switching, and arbitrary waveform response.
Created a unified parameter-extraction approach using P–V, C–V, and recoil measurements.
Implemented stochastic multidomain switching with distributed activation fields.
Added separate intrinsic dielectric and domain-wall response times.
Developed charge-based equations suitable for Verilog-A and SPICE simulation.
Validated the model across large-signal and small-signal operating conditions.
MATLAB for numerical model development, parameter extraction, and waveform simulation.
Verilog-A for compact-model implementation.
Cadence Spectre / SPICE for device–circuit simulations.
Python for data processing, optimization, and visualization.
Ferroelectric Analyzer Data for P–V, C–V, switching-current, recoil, and frequency-dependent calibration.
Optimization Algorithms for multidimensional parameter fitting.
HZO MFM FeCAP Measurements for experimental validation.
FeRAM Circuit Simulation: Predicting write behavior, read disturbance, sensing margin, and endurance-related operating conditions.
Non-Destructive Capacitive Read: Modeling polarization-state-dependent capacitance without requiring polarization reversal.
Compute-in-Memory: Simulating charge-domain multiply–accumulate operations using programmable FeCAP states.
Analog and RF Circuits: Studying voltage-tunable capacitance, dielectric loss, and frequency-dependent response.
SRAM Write Assist: Evaluating ferroelectric-capacitor-assisted voltage boosting and energy reduction.
Device–Circuit Co-Design: Connecting material properties, domain dynamics, waveform conditions, and circuit performance.
This project addresses a major limitation of existing ferroelectric compact models: the inability to consistently predict both large-signal switching and small-signal capacitance using a single physical framework. By coupling multidomain switching with reversible dielectric and domain-wall dynamics, the model enables simulations across DC, transient, and frequency-dependent operating regimes.
The framework also provides a physical explanation for why small-signal C–V measurements are primarily controlled by reversible domain-wall displacement, while large-signal P–V measurements are dominated by irreversible domain switching. This distinction is important because large-signal and small-signal measurements probe fundamentally different polarization processes.
