Md Sadik Yasir Tauki - 1T-nC vs 2T-nC FeRAM Reliability Trade-offs

1T-nC vs 2T-nC FeRAM Reliability Trade-offs
Mixed-mode TCAD and SPICE modeling for scaling, parasitics, and disturb analysis

Project Overview
This project presented a comparative study of 1T-nC and 2T-nC FeRAM architectures under aggressive dimensional scaling (XY/Z) and vertical stacking, highlighting the trade-offs in sense margin, parasitic effects, and read reliability. Using Sentaurus TCAD (SDE, Device, Workbench, Mixed-Mode) integrated with SPICE-level simulations in Cadence Spectre, the work established design guidelines for scalable, high-density FeRAM arrays.

Key Features
💾 Architecture Comparison: 1T-nC destructive read vs. 2T-nC quasi-nondestructive read
📐 Scaling Studies: XY, Z, and XYZ scaling in 3D capacitor arrays
🔌 Parasitic Extraction: Modeled vertical, diagonal, and lateral coupling capacitances from TCAD structures
⚡ Mixed-Mode Simulation: Coupled TCAD ferroelectric device models with transistor models (PTM16) for circuit-level validation

Research Contributions

Developed full Sentaurus TCAD workflow: 3D capacitor stack construction (SDE), meshing, parasitic extraction, and mixed-mode simulation with CMOS devices.
Identified sense margin collapse in 1T-nC due to destructive reads and large bitline parasitics, vs. stable low-voltage sensing in 2T-nC enabled by transistor isolation
Proposed floating-node capacitor isolation to decouple sense margin from stack height (n), improving both 1T- and 2T-nC reliability
Conducted Monte Carlo variation study (±10% geometry, CBL, Vth) showing tighter margin distribution and robustness in 2T-nC

Technical Achievements

Modeled up to 256 stacked capacitors per cell in TCAD with realistic parasitic networks
Demonstrated >2× stronger and more stable sense margin in 2T-nC compared to 1T-nC under aggressive scaling
Validated readout behavior under non-ideal isolation resistance (100 MΩ–TΩ), highlighting reliability limits for large arrays
Published results in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC, 2025)

Applications

3D FeRAM architectures for high-density memory
Logic-in-memory / Compute-in-memory systems leveraging reliable 2T-nC cells
Device–circuit co-design frameworks combining TCAD, SPICE, and system-level evaluation

Impact and Recognition
This project established TCAD–circuit co-simulation methodologies as a powerful framework for evaluating FeRAM scaling limits and guiding architecture selection. The results provided actionable insights for energy-efficient, reliable memory design and were recognized with publication in IEEE JXCDC (2025)

(a) TCAD model of nine vertically stacked ferroelectric capacitor strings, (b) corresponding circuit schematic representation, and (c) reference design parameters employed for TCAD simulations.

(a) Overview of 1T-nC (destructive read) and 2T-nC (QNRO) FeRAM architectures. (b) Three-dimensional schematic of 1T-nC FeRAM with vertically stacked capacitors sharing a single transistor. (c) 2T-nC FeRAM with two access transistors enabling improved read reliability and sense margin.