Understanding Reliability Trade-offs in 1T-nC and 2T-nC FeRAM Designs
Sadik Yasir Tauki,Rudra Biswas,Rakesh Acharya,Jiahui Duan,Rajiv Joshi,Kai Ni,Vijaykrishnan Narayanan || accepted at IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Ferroelectric random-access memory (FeRAM) is a promising energy-efficient non-volatile memory for logic- and compute-in-memory applications. This work compares 1T-nC and 2T-nC FeRAM architectures under dimensional scaling (XY/Z) and vertical integration. Using TCAD and circuit-level simulations, we analyze the impact of scaling on ferroelectric capacitance, parasitic coupling, and floating-node dynamics, which dictate sense margin and read stability. A floating unselected capacitor strategy effectively decouples sense margin from stack height, enabling analysis across scaling regimes. Results show that 1T-nC suffers more from bitline charge sharing, while 2T-nC gains robustness from transistor isolation and stronger low-voltage sensing at the expense of area. This study establishes the reliability trade-offs of both architectures and provides design guidelines for high-density 3D FeRAM.
Towards Scalable 3D Integration of 2T-nC FeRAM with Hundreds of Layer Stacking
Jiahui Duan, Shan Deng, Rudra Biswas, Sadik Yasir Tauki, Sizhe Ma, Rajiv Joshi, Thomas Kampfe,Xiao Gong, Vijaykrishnan Narayanan, and Kai Ni|| accepted at 𝐈𝐄𝐃𝐌 2025
https://doi.org/10.1109/IEDM50572.2025.11353513
In this work, we investigate the scaling limits and read-history dependence of 2T-nC FeRAM cells to enable high-density integration with hundreds of stacked capacitors. Through combined experiments and simulations, we show: (i) successful fabrication of 2T-64C cells with robust operation and clear ‘0’/‘1’ states; (ii) the floating-node parasitic arises mainly from the linear ferroelectric capacitance, with sense margin degradation mitigated by floating unselected capacitors under TΩ isolation; (iii) sharing write/read transistors across n capacitors introduces read history dependence via fluctuating VFN; and (iv) a floating-node discharge scheme effectively removes sequence dependence, at the cost of reduced read endurance.
Vertical 2T-nC FeRAM Demonstration: BEOL Read Transistor for 4F2 Memory Strings and Two-Terminal Selector Design for Polarization Disturb Mitigation
Shan Deng, John Howe, Sizhe Ma, Sadik Yasir Tauki, Zijian Zhao, Jiahui Duan, YuShan Lee, Yixin Qin, Rajiv Joshi, Thomas Kampfe, Xiao Gong, Vijaykrishnan Narayanan, Kai Ni || 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
https://doi.org/10.23919/VLSITechnologyandCir65189.2025.11074964
In this work, we demonstrate a vertical 2T-nC FeRAM with a back-end-of-line (BEOL) read transistor (TR) for 4F2 string and propose a selector design to mitigate polarization disturb in passive capacitor crossbar arrays. Key contributions include: 1) successful integration and operation composed of a Si MOSFET write transistor (TW), 3-layer cylindrical ferroelectric capacitors, and Si-doped In2O3 BEOL TR, demonstrating the feasibility of 4F22T−nC string; 2) introducing nonlinearity into the capacitor stack to suppress ferroelectric voltage drop under inhibition biases while maintaining sufficient write voltage, reducing disturbance; 3)modeling and experimental validation of inserting a metalsemiconductor (a-Si)-metal (MSM) selector into the capacitor in mitigating the disturb, particularly achieving 9x reduction of disturb after 106 cycles in the VW/2 scheme.
MIND-MAC: Multi-Level In-memory Quasi Non-Destructive MAC Operation in Compact 2T-nC FeRAM for Efficient DNN Accelerator
Rudra Biswas1 , Varun Parekh1 , Prapti Panigrahi1 , Sadik Yasir Tauki1 , Jiahui Duan2 , Shan Deng2 , Kai Ni2 , and Vijaykrishnan Narayanan1 || 2025 Non-Volatile Memory Technology Symposium (NVMTS)
We present MIND-MAC, a compact 2T-nC FeRAM architecture that performs multi-level, quasi-non-destructive in-memory multiply–accumulate (MAC) for deep neural networks. By exploiting voltage-controlled partial domain switching in MFM capacitors and read-transistor amplification, the cell stores multi-bit weights and gates bit-serial inputs to produce an accumulated current on shared lines. We combine TCAD-extracted parasitics with experimentally calibrated ferroelectric models in SPICE to validate device-/circuit-level behavior, and validate multi-level sensing and QNRO with measurements on a fabricated 2T-3C test vehicle. An analytical system model maps MIND-MAC to a 6-GB main-memory in-memory compute (IMC) architecture and benchmarks VGG13 inference in 61.08 ms at 964.99 mJ. Results indicate high density, reduced rewrite overhead, and energy efficiency, positioning 2T-nC FeRAM as a promising IMC candidate for next-generation AI hardware.
Modeling Second Order Anisotropy of Monodomain Magnetic Body.
Sadik Yasir Tauki, Orchi Hassan || ICECE 2022
Paper Presentation at ICECE-2022
We present a SPICE-compatible model of a monodomain magnet based on LLG equation which includes the second order anisotropy effect. Surface asymmetry due to miniaturization of devices leads to higher order anisotropy increment, and so an accurate model of magnetization dynamics is required to calculate higher order contribution. Our investigation of the critical switching field and current of a 40 kBT and 60 kBT perpendicular anisotropy magnet revealed that there is significant contributions from the second order anisotropy, especially when it becomes comparable to the first order anisotropy parameters. So, for future study of magnetic devices, second order anisotropy value should be considered. We believe our model is useful in advancing the study of magnetization dynamics of perpendicular magnetic anisotropy (PMA) magnets as well as in-plane magnetic anisotropy (IMA) magnets. As it includes noise in the system, it is also suited to study low-barrier magnet dynamics. The modular nature of the model allows it to be readily extended to include any physical magnetic phenomenon. The SPICE-compatible aspect also allows it to be easily adapted into the integration and co-design of CMOS and spintronics based circuits and systems.