Research Areas

My research bridges emerging memory devices, VLSI circuit design, and system-level architectures to build scalable, energy-efficient computing platforms. I combine device modeling, circuit verification, and RTL/architecture-level design to enable practical deployment of ferroelectric and other next-generation memory technologies. I am particularly interested in:

Ferroelectric Memories & Emerging Devices

• Modeling and scaling of 1T-nC, 2T-nC, and 3D-stacked FeRAM architectures

• Designing selector-integrated FeCAP/FeRAM arrays for enhanced reliability and disturb mitigation

• Exploring FeFET multi-level cells for logic-in-memory and compute-in-memory (CIM) applications

• Investigating spintronic and thin-film transistor technologies for novel non-volatile memories

Circuit Design, VLSI & RTL Systems

• Developing multi-level sensing circuits and charge-domain CIM architectures

• Integrating TCAD-based device models into SPICE/Verilog-A and Cadence Spectre workflows

• Performing Monte Carlo and temperature studies for robust circuit performance

• RTL design, testbench development, FPGA prototyping, and VLSI/EDA flow integration for memory and accelerator systems

System & Architecture Exploration

• Evaluating 3D ferroelectric memory stacks for high-density, high-performance computing

• Analyzing trade-offs in sense margin, energy, and throughput across architectures

• Designing systolic arrays and accelerator architectures for DNNs and bioinformatics workloads

• Bridging device–circuit–architecture co-design to advance scalable compute-in-memory solutions

Academic Background

I am currently pursuing a Doctor of Philosophy (Ph.D.) in Computer Science and Engineering at Pennsylvania State University, where I work under the guidance of Prof. Vijaykrishnan Narayanan. My doctoral research focuses on ferroelectric memory technologies, device–circuit co-design, and compute-in-memory architectures, with an emphasis on scaling, reliability, and 3D integration for next-generation energy-efficient systems.

Before beginning my doctoral studies, I completed a Bachelor of Science in Electrical and Electronic Engineering at the Bangladesh University of Engineering and Technology (BUET). My undergraduate training provided a strong foundation in semiconductor device physics, digital and analog circuit design, and VLSI systems, and I conducted early research in device modeling and spintronic memory.

This combined background in devices, circuits, and architectures has equipped me with the interdisciplinary expertise needed to advance emerging memory technologies from physical models to practical computing systems.

Technical Expertise 

Programming & Simulation

• Python, MATLAB, C, C++

• Verilog/VHDL, Shell scripting, Wolfram

• Machine learning frameworks (PyTorch, TensorFlow, Pandas, NumPy, JMP, Jupyter, LaTeX)

• Neuromorphic and compute-in-memory simulation tools

EDA Tools & Circuit/Device Simulation

• Synopsys Sentaurus Suite: SDE (structure editor & meshing), SDevice, Mixed-Mode, Workbench, Inspect/Visual 

• Cadence Virtuoso, Spectre, HSPICE, ModelSim, Quartus

• Synopsys Design Compiler, PrimeTime, VCS

• COMSOL Multiphysics, Simulink, PSpice, Proteus, 8086 Emulator, Arduino

VLSI & Digital/ASIC Design

• RTL design and verification, FPGA prototyping, testbench development

• Logic synthesis, Place & Route, Static Timing Analysis (STA), Timing closure, DFT

• SRAM/DRAM design and optimization, CMOS/FinFET circuit design

• Device–circuit co-simulation and multi-level sensing circuits

Analog/Mixed-Signal Circuits

• Op-amp and comparator design

• Biasing circuits, current mirrors, and amplifiers

• ADC/DAC, filters, and noise analysis

Device R&D & Emerging Technologies

• Ferroelectric devices (FeRAM/FeFET), NVM, SRAM/DRAM

• Selector-device integration for FeCAP/FeRAM arrays

• Spintronic devices and thin-film transistor (TFT) modeling

• Parameter extraction and Verilog-A compact modeling

Hardware & Laboratory Skills

• PCB design, lab instrumentation (oscilloscope, signal generator, PLCs)

• Device characterization: probe station, Keithley/Keysight instruments with LabVIEW

AI & Advanced Computing

• Proficiency in generative/agentic AI tools: Cursor, GitHub Copilot, VSCode, Cline, ChatGPT Agents

• Prompt engineering for research, code development, and teaching workflows

• Hardware–software co-design for edge AI optimization

Collaboration & Tools

• Git, Slack, Microsoft Office, Google Workspace

Research Impact & Publications

My research advances the field of ferroelectric memory and compute-in-memory architectures, bridging device-level physics with circuit design and system evaluation. I have developed mixed-mode TCAD and SPICE models to explore reliability trade-offs in FeRAM, introduced selector-device integration strategies for suppressing disturbances in large-scale memory arrays, and demonstrated the potential of multi-level in-memory MAC operations for efficient deep learning accelerators. 

Teaching & Mentorship

As a Graduate Mentor in Penn State’s SROP program, I have supervised undergraduate projects in digital design, circuit verification, and emerging memory modeling, helping students build both theoretical understanding and hands-on skills.

Previously, I served as a Lecturer at the Bangladesh University of Textiles, where I taught Digital Circuit Design (Verilog, FPGA, and logic synthesis) and developed laboratory modules for RTL coding, functional verification, and device physics experiments. I am passionate about making advanced concepts in memory design, VLSI, and device–circuit co-design accessible to students and fostering the next generation of semiconductor researchers

Vision & Future Directions

I envision a future where emerging memory technologies like FeRAM and FeFET form the backbone of energy-efficient computing. My goal is to push the boundaries of device–circuit–architecture co-design, enabling:

• Scalable 3D memory systems with improved density and reliability,

• Compute-in-memory accelerators that transform workloads in AI, bioinformatics, and edge computing, and

• Hybrid architectures that merge ferroelectric, spintronic, and neuromorphic devices into adaptive, low-power platforms.

By uniting innovations in VLSI, RTL design, and device modeling, I aim to build memory-centric architectures that address the energy and scaling challenges of future intelligent systems.