Scalable 3D 2T-nC FeRAM with Hundreds of Layers
TCAD–SPICE co-simulation of parasitics, scaling, and read-disturb reliability
Project Overview
This project investigated the scalability of 2T-nC FeRAM architectures toward hundreds of stacked ferroelectric capacitors per cell, combining 3D Sentaurus TCAD modeling with Cadence Spectre circuit simulations. The goal was to quantify how floating-node parasitics, XY/Z scaling, and read-history effects impact sense margin and readout reliability in high-density vertical arrays
Key Features
🏗️ Sentaurus TCAD (SDE/Device/Workbench): Constructed 3D capacitor stacks (up to 256 layers), extracted coupling capacitances (CFE, CX, CY, CXY) under XY/Z scaling
🔌 Parasitic-Aware Circuit Models: Exported TCAD-derived capacitances into compact Verilog-A/SPICE netlists
⚡ Mixed-Mode Co-Simulation: Coupled TCAD ferroelectric device models with PTM16 transistor models in Cadence Spectre to simulate full read/write paths
📉 Read Disturb Analysis: Modeled grounded vs. floating unselected capacitors and finite selector resistance (100 MΩ–TΩ) on sense margin stability
Research Contributions
Built parametric TCAD SDE structures to analyze electrostatic coupling in large FeCAP strings
Identified linear growth of CFE with stack height, leading to collapsing sense margin in grounded arrays
Demonstrated floating unselected capacitors with selector isolation preserve sense margin across 64C–256C stacks
Implemented Cadence Spectre mixed-mode simulations validating TCAD predictions with transistor-level IRBL readout circuits
Proposed a discharge-before-read scheme to remove read-history dependence, validated through TCAD–Spectre co-simulation
Technical Achievements
Extracted TCAD parasitics for up to 256-cap stacks and integrated into circuit netlists
Verified readout robustness in 2T-16C and 2T-64C experimental prototypes, matching TCAD+Spectre predictions
Showed >2× stronger and more stable sense margin in 2T-nC vs. 1T-nC under scaling and parasitic loads
Demonstrated device–circuit co-design flow linking Sentaurus TCAD, Verilog-A, and Cadence Spectre as a reusable methodology
Applications
3D non-volatile memories with higher density and reliability than planar FeRAM
Compute-in-memory accelerators requiring large-array stability
Cross-domain design frameworks integrating TCAD parasitics into SPICE-level architecture evaluation
Impact and Recognition
This project showcased a complete TCAD-to-SPICE design pipeline, proving that accurate parasitic extraction and mixed-mode co-simulation are essential to evaluate FeRAM reliability at scale. The results defined new design guidelines for hundreds-layer FeRAM integration and were recognized with publication at IEEE IEDM 2025
