Systolic Array Optimization for Neural Network Acceleration
Evaluating hardware utilization and performance trade-offs using SCALE-Sim

Project Overview
This project explored systolic array architectures for accelerating deep neural network workloads using SCALE-Sim v2. By experimenting with different array sizes (12×12, 32×32, 64×64, 128×128, 256×256) and dataflows (Input Stationary, Output Stationary, Weight Stationary), the study aimed to optimize the area-delay product—balancing performance in cycles with hardware utilization