This theme explores 2D material-based CFET CMOS integration as a promising path beyond conventional silicon scaling. By vertically stacking n- and p-type devices, the approach enables higher density and improved performance within a reduced footprint. The work systematically addresses key challenges in integration, gate dielectric scaling, and contact engineering, aiming to achieve efficient device operation and reliable system performance. Together, these efforts pave the way toward optimal power, performance, and area (PPA) for next-generation computing technologies.