© nemo 2002-2020
WriteReg is a debugging module that displays the contents of any register, or the processor flags.
The current version is 1.09 (26 November 2021) [32bit]
This version is not compatible with RISC OS 6.
This module provides a number of SWIs for displaying the contents of any register without side-effects. As well as the usual parameter registers it can display R10-R15, plus the flags, CPSR and SPSR. It will even display the SWI’s X Flag... because it can.
Important: As of 1.09 it now preserves ALL flags on exit, including V. This means you need to call the X form of the SWIs if there’s any possibility of the V flag being set on entry, or the kernel’s SWI Handler will call the Error Handler on exit. (and StrongARM or later is now required)
RISC OS 5 has a history of either misunderstanding APIs or unilaterally deciding to retrospectively change them in incompatible ways, and 5.24 is no different. Previous versions misinterpreted error numbers (and hilariously generated an error claiming that the error was erroneous). But 5.24 has gone further, deciding to break the API contract specified on RPM page 1-26 which states:
As the [SWI] exits, RISC OS checks the V flag. If it is set[...] then RISC OS looks at bit 17 (the X bit) of the SWI number: If it is set then control returns to your program, and you should deal with the error yourself.
5.24 changes this. If the V flag is set on exit and the X bit was set in the SWI, it may decide to corrupt R0 entirely. It does this because some RO5 developer decided that they knew better than the author of the module and the author of the code calling it, and that thirty years of compatibility can be thrown away because of how very clever that one person is.
I’m sick to the back teeth of dealing with the consequences of people messing with things they don’t understand, so I now no longer regard RO5 as a RISC OS compatible operating system. It is somewhat compatible, but is evidently not guaranteed to stay so.
I will henceforth refer to it as DKOS.
Write_R0 - Write_R15
Displays the contents of the caller’s register. In the case of R14 and R15 in 26bit modes, this will include flags. The value is displayed as an 8 digit hexadecimal number followed by a space.
Displays the caller’s PC in hex. This never includes flags.
Displays all of the caller’s registers in a 4×4 grid.
Displays registers selected by R8, in up to a 4×4 grid. R8b0 set displays R0, b1 displays R1, and so on.
Displays the flags and mode in hex.
Displays the caller’s flags as four characters followed by a space.
Displays the CPSR and SPSR in hex on those processors that support them.
Tells you in hex whether you called Write_X or XWrite_X. This is more clever than useful.
RISC OS 6
RO6 contains a significant change to stack handling which severely complicates low-level things like WriteReg and VectorExtend. I have chosen to not support it because of this. However, I am open to persuasion if there’s anyone out there running Six. I suspect that the vast majority of users have RO5 on new hardware or RO4 on an emulator.