SV
UVM を使った検証環境のトップモジュールの例
// top module
#include " .sv" // include UVM package
#include "my_apb_if.sv" // include interface definition
#include "my_kkk_if.sv"
#include "my_xx_pkg.sv" // include package of agent x
#include "my_yy_pkg.sv" // include package of agent y
module tb_top ;
import uvm_pkg::*; // import UVM resource
include "uvm_macros.svh" // import UVM marco
import my_xx_pkg::* ; // import agent resource
import my_yy_pkg::* ;
logic clk, rst_n ; // clock, reset signals
// interface instances
my_kkk_if my_kkk_if ( clk, rst_n ) ;
// DUT instances
dut_wrap dut ( clk, rst_n, my_kkk_if, ... );
// include tests
`include "test_list.sv"
// clock, reset generation
always #500ns clk = ~ clk ;
initial begin
# 1 rst_n = 1'b0 ;
#1000 rst_n = 1'b1 ;
end
// initial for UVM
initial begin
// config db set of virtual interface
uvm_config_db # ( virtual my_kkk_if ) :: set (
null, "*", "vif", my_kkk_if ) ;
// start UVM phases
run_test ( );
end
// SVA module definitions and bind
// waveform generation, etc.
initial begin
$fsdbDumpfile ( "my.fsdb" );
$fsdbDumpvars ( 0, tb_top ); // up to bottom
$fsdbDumpon ();
end
endmodule
ディレクトリ構造の例
+- rtl // DUT
|
+ verif
+- sim
| +- Makefile // work dir for run
|
+- env
| +- xx // directory for each agent
| | +- package, agent, sequencer, driver,
| | sequence_item, monitor
| +- yy
| +- interface
| +- env, test(base), top
|
+- tests
| +- test_list, seq, test
+- sva
+- fcov