SV
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====== Synopsys VIP 共通
=========================================================
Docs
axi_svt_uvm_user_guide.pdf
Synopsys
https://www.synopsys.com/apps/japan/today-tomorrow/articles/tt106-eda-tools-verif-howto.html
https://www.vmmcentral.com/uvm_vmm_ik/
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環境設定 (VCSを使用する場合)
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//----------------------------------
// setup
//----------------------------------
setenv VCS_VER L-2016.06-SP2-1
setenv VCS_HOME <vcs-path>/${VCS_VER}
setenv VCS_UVM_HOME ${VCS_HOME}/etc/uvm-1.1
setenv VCS_LICENSE_WAIT 1
setenv DESIGNWARE_HOME <design_ware_path>
set path=(${DESIGNWARE_HOME}/bin ${path})
license file setting
//----------------------------------
// install
//----------------------------------
# Install AMBA VIPs.
dw_vip_setup -path <path> -add axi_system_env_svt -svlog
dw_vip_setup -path <path> -add apb_system_env_svt -svlog
例
dw_vip_setup -path ./amba_vip -add axi_system_env_svt -svlog
dw_vip_setup -path ./amba_vip -add apb_system_env_svt -svlog
# Install AMBA VIP examples.
# 例をローカルのディレクトリにコピーする。必須ではない
dw_vip_setup -path <path> -example amba_svt/tb_axi_svt_uvm_basic_sys -svtb
dw_vip_setup -path <path> -example amba_svt/tb_apb_svt_uvm_basic_sys -svtb
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ツールのオプション (VCSを使用する場合)
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//----------------------------------
// build
//----------------------------------
// vlogan_opt
-sverilog
-ntb_opts uvm
-kdb
+define+SYNOPSYS_SV
+define+SVT_UVM_TECHNOLOGY
+define+SVT_AXI_INCLUDE_USER_DEFINES // required for AXI VIP
+define+SVT_APB_INCLUDE_USER_DEFINES
+define+UVM_PACKER_MAX_BYTES=1500000 // required for AXI VIP
+define+UVM_DISABLE_AUTO_ITEM_RECORDING // required for AXI VIP
+libext+.v+.sv +warn=all (only vlogan)
-debug_access+all
+incdir+${AMBA_VIP_DIR}/include/sverilog
+incdir+${AMBA_VIP_DIR}/src/sverilog/vcs
(AMBA_VIP_DIR = ./amba_vip, for example)
-timescale=1ps/1ps (only vlogan)
// vcs
-lca +vcs+lic+wait
//----------------------------------
// run
//----------------------------------
do_opt="-do ${TEST_DIR}/script/do.tcl"
-ucli
${do_opt}
+UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW
+UVM_TESTNAME=<test name to be executed>
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SystemVerilog ソース 準備
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//----------------------------------
// パッケージの挿入(topの外側)
//----------------------------------
// Include uvm package before VIP includes, if not included elsewhere.
`include "uvm_pkg.sv"
// Include AXI and APB SVT UVM packages.
`include "svt_axi.uvm.pkg"
`include "svt_apb.uvm.pkg"
//----------------------------------
// インターフェイス定義の挿入(topの外側)
//----------------------------------
// Include AXI and APB VIP interfaces.
`include "svt_axi_if.svi"
`include "svt_apb_if.svi"
//----------------------------------
// パッケージのimport(topの中)
//----------------------------------
module TB;
// Import UVM package.
import uvm_pkg::*;
// Import SVT UVM package.
import svt_uvm_pkg::*;
// Import AXI and APB VIP packages.
import svt_axi_uvm_pkg::*;
import svt_apb_uvm_pkg::*;
//----------------------------------
// マクロ設定の変更
//----------------------------------
例：
APB信号のビット幅はマクロで定義する
`define SVT_APB_PWDATA_WIDTH 32
`define SVT_APB_PRDATA_WIDTH 32
物理的な信号の幅はこれで定義し（つまり最大値)、
cfg は実際に使われるビット幅？