SV
- property PRO
@(posedge clk) (property descriptions)
end property
assert property (PRO) error if false
- property operator
- disable iff(b) if b is true, this property is true ignoring other conditions
- SA1 -> SB sequence SB is in the same cycle as SA1
- SA1 => SB sequence SB occurs in the next cycle of SA1
- assertion label
label_if: assert property (property_name@(arg))
- creating assertion
1. define a module for assertion
2. bind it to testbench (bind top assertion_module I_assert_mod)
- see sim.log for assertion messages
connectivity check には即時アサーションが使える
S0 |=> S1 : non overlap
S0 |-> S1 : overlap (S0の最後とS1の最初が同一クロックサイクル)
即時アサーションは initial, always 中で使える。task 内でも
if が代用できるので、あまり使わない方がいい
default clocking NN@(posedge clk) endclocking