SV
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IP
* proc_sys_reset (Processoro System Reset Module) (pg164)
DCM Locked input (DCM = Digital Clock Manager, Xilix 用語?)
POR: all reset become active within first two clocks of a power up, remain for 16 clocks
Sequence
bus/interconnects -> (16 cycles) -> peripherals (16 cycles) -> MicroBlaze
Active Window Width (for External and Auxillary resets)
if width is 5, ext_reset_in must be active at least 5 clocks before a reset is initiated.
mb_debug_sys_rst: 通常 MDM(Microprocessor Debug Module) に接続。config 効かない
dcm_locked: DCM を使用していないときは、high に固定。
slowest_sync_clk: システム中最も遅いクロック (AXI4-Liteがよく使われる)
bus reset に使うので bus clock をつながないといけない
* CDMA (CentralDMA)
memory mapped source -> destination (AXI4) (AXI4-Lite slave for control)
SG (Scatter Gather) option, dedicated AXI4 I/F
AXI4 master (32,...,1024)
little endian
BD (Buffer Descriptor)
Interrupt
when Simple DMA mode, transfer is completed.
http://www.xilinx.com/support/documentation/application_notes/xapp1168-axi-ip-integrator.pdf
http://japan.xilinx.com/support/documentation/application_notes/j_xapp1168-axi-ip-integrator.pdf
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SDK
Flash Memory Programming
Cable & Device options
-cable type <type> esn <Electronic Serial Number> url <URL of server>
-debugdevice deviceNr <postion in jtag chane starting from 1>
launch_sdk -workspace H:/w4/sw/ws -hwspec H:/w4/hw/zybo_2016_2/zybo_2016_2.sdk/ZYBO_TOP.hdf
(command line when launched by Vivado)
Flash
BOOT.bin の ZYBO.QSPI への書き込み方
1. SDK の Xilinx Tools- Program Flash を選択する
2. Wizard が立ち上がるので以下の設定を行う
- Hardware Platform を ZYBO_TOP_hw_platform_0 にする
- Connection を Local にする
- Image File を H:\w5\sw\ws\vboxserver\bootimage\BOOT.bin にする
- Flash Type を qspi_single にする
3. Program を押す
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Vivado debug
デバッグする HDL 信号のマーク
合成 [Run Synthesis]
合成済みデザインでデバッグ用のネットをマーク
[Synthesis Design] [Debug] View
Set Up Debug wizard ([Debug] View の方が詳細に設定できる）
デバッグコアのプロパティ変更
ILA コア選択、property view (Cell Properties) -> debug core options
C_DATA_DEPTH (sampling times)
Implementation
Vivado でも VIO(Virtual IO)はサポート。ICONコアの挿入不要。ILA(Integrated Logic Analyzer のみ)
Program
Hardware Manger -> Open Target -> Program Device (bit, *.ltx)
Set Up Debug で一旦消す
再び Wizard
Find Nets to Add, Properties -> MARK DEBUG
C_USER_SCAN_CHANE 3
program しても device に debug core が入ってない。
VIO削除してみる
だめ
たまにうまくいく
Hardware Manager
ILA Core Properties
Trigger Position を 512 (1024の中間)にする
Trigger Setup
+ で信号追加 Compare Value
GUI で * をつけるのではなく、
RTL に (* mark_debug = "true" *) と書いた方が便利。
他のツールだと通らないかもしれないが
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Vivado batch
ug892-vivado-design-flows-overview.pdf
% vivado -mode batch -source <your_Tcl_script>
project-mode and non-project-mode
read_verilog is non-project-mode command
tcl saved with write_project_tcl is project-mode type.
write_project_tcl saves the tcl in the below dir
=> C:\Users\a_mizuno\AppData\Roaming\Xilinx\Vivado
* project mode command
create_project
add_files
set_property
launch_runs / launch_runs -to_step
* project mode typical flow
- create project
- manage source files
- IP (manage IP location, configure IP catalog, generate IP, synth IP out-of-context)
creating IP subsystem block design (package, upgrade)
* command
get_projects [...] [<patterns>]
Return list of open projects that match the specified patterns. The default gets all.
create_project [-part <arg>] [...] [<name>] [<dir>]
set_property <name> <value> <objects>...
create_property
get_property [...] <name> <object>
list_property [...] [<object>] [<patterns>]
list_property_value
report_property
reset_property
version [-short] [-quiet] [-verbose]
-short: Return only the numeric version number
create_bd_addr_seg -range <arg> -offset <arg> [<parent>] [<slave>] <name>
Create master?? address segment
* property
\\CENT07\project\public\11_検証製品事業部\81_Specification\xilinx\UsersGuide
ug835-vivado-tcl-commands.pdf
ug912-vivado-properties.pdf
ug892-vivado-design-flows-overview.pdf => Project Mode (Ch.2)
ug984 => あまり情報なし
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Vivado sim <-> Other vendors' sim
ug900-vivado-logic-simulation.pdf
Go to http://www.xilinx.com/support.html and serch with it.