Machine Learning-based Test Quality Improvement for Integrated Circuits

The design and manufacturing flow of integrated circuits includes various processes to improve dependability, such as wafer test, burn-in test, package test, speed binning, failure analysis, test facilitation design, and test generation.

In wafer and package testing, numerous test items are tested at multiple temperature settings, and only chips that pass all test items are allowed to proceed to the next process. In burn-in testing, potential faults are manifested by testing under stress conditions such as high temperature and high pressure. Potential faults are faults that, without burn-in, would have passed all tests and been shipped, and which could manifest themselves early in the life of the product. Performing burn-in testing improves the reliability of products in which integrated circuits are embedded. Fault diagnosis provides a detailed analysis of chips that fail in various tests and feedback to the design and manufacturing flow to improve product quality.

Integrated circuits can operate at high speeds with low power consumption as transistors, the building blocks of integrated circuits, are miniaturized. On the other hand, the high degree of integration increases the number of transistors on a chip, making testing by accessing only the external pins a complex and costly problem. Therefore, research is being conducted on design for testability, which is a design modification to facilitate testing, and on test generation algorithms that generate test patterns to achieve high-quality testing at low cost.

Increased test cost and test escape are becoming problems due to larger circuits caused by miniaturization, increased transistor variation, and excessive power during testing. The Dependable Systems Laboratory is addressing technologies to reduce test cost and improve test quality using machine learning. Specifically, we are conducting research to reduce the cost of burn-in testing by predicting the results of costly burn-in tests before testing, and to improve product quality by predicting test escapes of defective products.