Embedded Files
Inmos Simple 42 Prototype Transputer Emulator
During September 2014 to March 2015 (and briefly tweaked in May 2021), I spent time writing a Inmos Simple 42 emulator. On this webpage is the Inmos Simple 42 (or S42 for short) emulator for the PC. The emulator is written in C and uses the output header file generated by the simple 42 assembler tool, in order to run the actual VBC code written by Inmos. The design of the emulator is based on the detailed block diagrams in this webpage, which are based on the Inmos documents recently made available by David May (see links in the VBC reader section). I have verified about 56% of the 46 instructions so far.
The following is a list of the instructions verified so far:
J, LDL, PFIX, NFIX, REV, GT, AND, OR, XOR, CLC, STAC, ADD, ADDC, SUB, SUBC, MUL, UMUL, DIV, UDIV, SEX, TLNG, LB, SL and SR.
Note: This is BETA SOFTWARE and not fully tested.
If you want to have a play with the Inmos S42 emulator you don’t actually need much set up in advance. Below is a brief overview of the software you will need to setup on your PC:
1. Copy the s42emu.exe binary file into a suitable directory on your computer, which is on the environment 'Path' setting.
2. To run the simple 42 emulator, enter the following:
s42emu /a /f s42_addc_ascii.txt
An example of the banner screen is shown below.
An example instruction file (ASCII format) and the executable file as attached at the end of this webpage. If there is interest I will make the source code available.
ToDo / Known Issues
The current Inmos Simple 42 emulator (version 0.9) has no known problems however there are still a number of instructions to be verified.
The current S42 emulator uses a byte read and write C function call for accessing memory during the LB and SB instructions, whereas the real Inmos S42 silicon used a 16-bit read modify write cycle to perform the SB instruction and a 16-bit read for the LB instruction. Hence memory access cycle timing for the SB instruction will not be correct in the emulator.
VBC Reader
During February to March 2014, I spent time writing a simple 42 microcode assembler (otherwise known as 'VBC reader'). It was based on documentation published by David May describing the Inmos 16-bit simple 42 prototype Transputer (documents are located here: dave's website).
Included in the data was the instruction microcode (or VBC) for the simple 42. It was a complete listing (well as best as I could work out at the time).
Anyway, I thought it would be fun to write a simple 42 microcode assembler (otherwise known as 'VBC reader' to ex Inmos employees) and see if I could assemble the simple 42 microcode available on Dave’s website.
Over the last few months I’ve converted the pdf copy of the microcode (or VBC) for the simple 42 into a text readable file. Written a simple 42 microcode assembler (approx. 2800 lines of C code), written numerous test cases (to test the assembler and its output) and finally I’ve successfully created a C header file which contains the complete simple 42 microcode ROM.
The simple 42 microcode assembler tool (a Win32 console application), a copy of the simple 42 microcode (aka VBC) (in text format) and the C header file output which contains the complete simple 42 microcode ROM (generated by the tool) are attached in the zip file at the bottom of this page.
To run the simple 42 assembler tool, enter the following and the s42ROM.h microcode ROM C header file will be created:
s42ma /f s42rev-vbc.txt
An example of the banner screen and the VBC reader in operation is shown below.
I’ve made the assumption the START: label must be located in the ROM at address 127, as I’m guessing that it’s the most likely place to jump to when the simple 42 powered up, based on a simple way to create 127 in hardware (i.e. all microcode bits 1 for address). Thanks to Jim Cownie for confirming that the START address could be moved with optimization - the ROM optimizer tool (one of two Inmos written special tools used for the ROM generation - the other being the VBC reader) switched addresses (except the entry point for instructions) to minimize the size of the ucode ROM. The idea was to remove empty space in the ucode address space to make the ROM smaller on the die.
Other interesting points are the empty locations (6 from 121 onwards), which means that the assembler correctly got 122 microcode instructions (as per the vbc) in the 128 size ROM, as described in the documentation on Dave's website.
Whilst generating the microcode assembly (using the simple 42 microcode assembler tool) I had to make a number of minor changes to the s42rev.vbc pdf listing at the bottom of the webpage, compared to the copy on David May's weksite.
Syntax Assumptions
The conditional select address label order is missing in the "microcode assembly language definition" section of the S42ENGDOC document.
Cond1fromxxx (Address_label, Address_label)
Cond0fromxxx (Address_label, Address_label)
Cond1fromxxx Cond0fromxxx (Address_label, Address_label, Address_label, Address_label)
Based on the review of the VBC (e.g. JNZ: and MUL: instructions) the following syntax was determined for the logic order verses the label order specified:
Cond1fromxxx Cond0fromxxx ([Addr,3], [Addr,2], [Addr,1], [Addr,0])
Cond1fromxxx ([Addr,2], [Addr,0])
Cond0fromxxx ([Addr,1], [Addr,0])
With:
Addr is feedback address for MIR[6..2] or MIR[6..1] depending if one or both conditional select drivers are used.
S42 Datapath Block Diagram
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
S42 Slave Registers Diagram
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
Shift Control Diagram
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
Destination Phase Disable Diagram
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
A and B Setting Multiplexor Diagram
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
C Setting Multiplexor Diagram
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
Incrementor Diagram
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
Microcontroller Diagram
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
Decoder
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
ucode ROM
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
ALU
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
ALU Carry In
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
S42 Divide Step Control Logic Diagram
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
S42 Multiply Step Control Logic Diagram
(The following diagram is based on data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above)
During my data digging on the internet, I uncovered an early Inmos patent US4724517 (see attached pdf file at bottom of page) for what appears to be the S43 or early Transputer predecessor, and more interestingly it does have an instruction set and simular architecture of the S42 so could be a useful document.
Inmos Simple 42 Plot
(The low resolution (2.7Mbytes) plot was provided courtesy of Brian Collins)
(The high resolution (9.3Mbytes) plot was provided courtesy of Brian Collins)
Inmos S42 Die Photograph
Photograph (medium resolution 4.2Mbytes) of the actual Inmos S42 die courtesy of Dave May and Miles Chesney, taken with the help of a PhD student and a microscope in Bristol's Nanoscience and Quantum Information Lab. The stitching of the 68 images back together was done by Miles. Nice job and I'm informed a higher resolution image is on it's way.
Using the unstitched images supplied on a CD by Miles Chesney (thanks again), I've created a number of higher resolution images which are now available for viewing on this webpage. I used Microsoft ICE and Gimp 2 to stitch, rotate and sharpen the final images.
A higher resolution photograph of the S42 die (130Mbytes) is available at at OneDrive to download.
Based on the 44 pads on the S42 plot and die above, I have determined the likely pin assignment was as follows:-
Note #1 - Thanks to Guy Harriman for confirmed that the S42 used word addressing for the external memory interface. Hence m.addr [0] likely unused. Only the SB store byte instruction needed to write a byte, and that was done by read modify write. The compiler word aligned strings so there was no cost in performance. The above signals are based on details defined in the Simple 7 documentation.
Note #2 - Boot pin discussed in S42ENGDOC section 2.1 (In documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May - link above). The boot pin was used along with the reset to determine booting method. Port 0 or extermal memory.
The plot of the S42 chip contains initials. They are:
IMB - Iann Barron
EEB - Eric Barton - worked on Fat Freddy
ICB - Ian Barton
BJC - Brian Collins (wrote early Occam compiler + HDL & Logic simulator)
HMC - Miles Chesney - (transputer design manager graphical design tools)
JHC - James Cownie (Jim wrote the VBC reader and ROM optimiser tools, and part of the Occam compiler)
ATF - Tony Fuge (or maybe AWF)
AWF - Andrew Ferris (or maybe ATF)
AHG - Alan Gray (wrote circuit analog simulator)
GH - Guy Harriman (wrote VBC ucode as well as logic design)
JJ - John Jakson (HW - focused on circuit design and layout using Fat Freddy mostly on the data paths)
DJM - David Munns (HW)
NS - Neil Shepherd (HW)
GS - Graham Steward (HW)
DW - Dave Wilson (CAD - worked on Fat Freddy and later on reticle production)
RPW - Richard (Chez) Watts (HW - logic design. John Jakson recalls that Richard actually drew up all the logic on a drafting board and the entire schematic fit on one large sheet)
On the actual S42 die (partial view above), photograph courtesy of Dave (davol) Wilson show additional initials:
MDM - David May (Transputer Architect)
PJC - Peter Cavill (HW manager)
RY - Rob Youngman (CAD).
UTC&A - is (obviously) Uncle Tom Cobbley & All.
Inmos S42 Design Team
Richard (Chez) Watts, Guy Harriman and John Jakson worked on the circuit design. Roger Shepherd worked with David May on architecture and instruction set architecture (ISA). Layout and CAD team are included in the initials above.
Why Simple 42 (or S42)
Guy Harriman explained to me that he was a fan of The Hitchhiker's guide to the galaxy when it was on the radio in 1978. The microcode used in the transputer prototypes (and for that matter the Production Transputers) was known as VBC which stood for 'Vogon Banana Code'. It was Guy's idea and Dave May went along with it.
The naming of the initial prototype transputer test designs, having started with S1, S2, S7, S15 ('simple 1' ... 'simple 15') suddenly jumped to S42. The S42 was (obviously) the answer to the Ultimate Question of Life, the Universe, and Everything! ;-)
The following section is currently work in progress. If anyone has knowledge of the S42 memory interface then please email me.
Simple 42 Memory Interface Overview Diagram
The following two block diagrams are based partly on the data within S42ENGDOC from documentation describing the Inmos 16-bit simple 42 prototype Transputer published by David May and on some ideas of how the interface worked having spoken with Guy Harriman, since actual circuit details are not documented.
Links to downloadable files:
Inmos S42 emulator (PC win32 build).zip
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