DE-Assignments

Assignment 1- PPT -Submission - Link 

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Reference:

1.  A Report in the Computing Curricula Series ,Joint Task Group on Computer Engineering Curricula, Association for Computing Machinery (ACM) , IEEE Computer Society, Version 2015 October 25 .

Assignment 2-Internal Assessment ( Pick any five section) 

Number systems and data encoding

1. Convert signed/unsigned, integer/fixed-point decimal numbers to/from binary/hex representations.

2. Perform integer/fixed-point addition/subtraction using binary/hex number representations.

3. Define precision and overflow for integer/fixed-point, signed/unsigned, addition/subtraction operations.

4. Convert signed/unsigned, integer/fixed-point decimal numbers to/from representation in the IEEE-754 floating-point standard.

5. Encode/decode character strings using ASCII and Unicode standards.

Boolean algebra applications

1. Define basic (AND, OR, NOT) and derived (e.g., NAND, NOR, XOR) Boolean operations.

2. Enumerate Boolean algebra laws and theorems.

3. Use basic and derived Boolean operations to evaluate Boolean expressions.

4. Write and simplify Boolean expressions by applying appropriate laws and theorems and other techniques (e.g., Karnaugh maps). 

Basic logic circuits

1. Describe electrical representations of TRUE/FALSE.

2. Describe physical logic gate implementations of basic (AND, OR, NOT) and derived (e.g., NAND, NOR, XOR) Boolean operations.

3. Describe the high-impedance condition and logic gate implementation such as a tri-state buffer.

4. Implement Boolean expressions using the two-level gate forms of AND-OR, OR-AND, NAND-NAND, NOR-NOR and positive/negative/mixed-logic conventions.

5. Implement Boolean expressions using multiple gating levels and positive/negative/mixed-logic conventions.

6. Discuss the physical properties of logic gates such as fan-in, fan-out, propagation delay, power consumption, logic voltage levels, noise margin, etc. and their impact on the constraints and tradeoffs of a design.

7. Discuss the need for a hardware description language (HDL) in digital system design.

8. Describe the logic synthesis process that transforms an HDL description into a physical implementation.

9. Implement combinational networks using an HDL and generate/verify using appropriate design tools.

History and overview

1. Identify some contributors to digital design.

2. Discuss applications in computer engineering that benefit from the area of digital design.

3. Describe how Boolean logic relates to digital design.

4. Enumerate key components of digital design such as combinational gates, memory elements, and arithmetic blocks.

Relevant tools, standards, and/or engineering constraints

1. Describe  design  tools  and  tool  flow  (e.g.,  design  entry,  compilation,  simulation,  and  analysis)  that  are  useful  for  the  creation  and  simulation of digital circuits and systems.

2. Discuss the need for standards and enumerate standards important to the area of digital design such as floating-point numbers (IEEE 754), character encoding (ASCII, Unicode), HDL standards (e.g., IEEE 1364 and IEEE 1076), etc.

3. Define important engineering constraints such as timing, performance, power, size, weight, cost and their tradeoffs in the context of digital systems design.

Modular design of combinational circuits

1. Describe and design single-bit/multi-bit structure/operation of combinational building blocks such as multiplexers, demultiplexers, decoders, encoders, etc.

2. Describe and design the structure/operation of arithmetic building blocks such adders (ripple-carry), subtractor, shifters, comparators, etc.

3. Describe and design structures for improving adder performance such as carry lookahead, carry select, etc.

4. Analyze and design combinational circuits (e.g., arithmetic logic unit, ALU) in a hierarchical, modular manner, using standard and custom combinational building blocks.

5. Implement combinational building blocks and modular circuits using an HDL and generate/verify using appropriate design tools.

Modular design of sequential circuits

1. Define a clock signal using period, frequency, and duty-cycle parameters.

2. Describe the structure/operation of basic latches (D, SR) and flip-flops (D, JK, T).

3. Describe propagation delay, setup time, and hold time for basic latches and flip-flops.

4. Describe and design the structure/operation of sequential building blocks such as registers, counters, shift registers, etc.

5. Analyze and create timing diagrams for sequential block operation.

6. Enumerate design tradeoffs in using different types of basic storage elements for sequential building block implementation.

7. Implement sequential building blocks using an HDL and generate/verify using appropriate design tools.

8. Describe the characteristics of static memory types such static SRAM, ROM, EEPROM, etc.

9. Describe the characteristics of dynamic memories.

10. Describe techniques (e.g., handshaking) of asynchronous design, and discuss its advantages (e.g., performance/power in some cases) and design issues (hazards such as race conditions, lack of tool support).

11. Describe the characteristics of advanced memory technologies such as multi-port memories, double data rate (DDR) memories, and hybrid memories (e.g., hybrid memory cube, HMC).

Control and data path design

1. Describe a digital system that is partitioned into control+datapath and discuss the need for control to sequence operations on a datapath.

2. Describe and contrast the different types of Finite State Machines (FSMs): e.g., Mealy State Machine, Moore State Machine, and Algorithmic State Machine (ASM).

3. Represent FSM operation graphically using a state diagram (e.g., Mealy state diagram, Moore state diagram, or ASM chart).

4. Analyze state diagrams and create timing diagrams for FSM operation.

5. Compute timing parameters such as maximum operating frequency, setup/hold time of synchronous inputs, clock-to-out propagation delays, pin-to-pin propagate delay for a control+datapath design.

6. Design/Implement a control+datapath design and generate/verify using appropriate design tools.

7. Discuss clock generation, clock distribution, clock skew in relationship to a control+datapath design.

8. Use pipelining to improve the performance of a control+datapath design. ƒ

9. Discuss applications that require serialization/de-serialization of bit streams, and implement a design that performs serialization/de-serialization.

Design with programmable logic

1. Describe basic elements of programmable logic such as lookup tables (LUTs), AND/OR plane programmable logic, programmable mux logic, and programmable routing.

2. Discuss programmable logic architectures such as Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs).

3. Describe common features of programmable logic architectures such as hard macros (e.g., adders, multipliers, SRAMs), clock generation support (e.g., PLLs, multiple clock networks), and support for different logic standards.

4. Implement a digital system in an FPGA or CPLD and describe and evaluate tradeoffs for implementation characteristics such as programmable logic resources that are used, maximum clock frequency, setup/hold times for external inputs, clock-to-out delay, etc.

5. Describe advanced features of programmable logic architectures in the form of hard macros such as CPUs, high-speed serial transceivers and support for other transceiver standards (e.g., PCI Express, Ethernet PCS, etc.).

System design and constraints

1. Compare and contrast top-down versus bottom-up design methodologies for system design.

2. Describe how to use logic synthesis timing constraints with an appropriate design tool for affecting logic generated for a control+datapath implementation.

3. Use constraints of clock-cycle latency and clock-cycle throughput to create alternate designs for a digital system.

4. Use other appropriate design tools (e.g., power estimator) for design space exploration and tradeoffs based on constraints such as performance, power, and cost.

5. Create an HDL-based self-checking behavioral test bench for a digital system design.

Fault models, testing, and design for testability

1. Describe the need for systematic testing methods in digital design.

2. Define fault models such as stuck-at, bridging, delay, etc.

3. Define the terms controllability, observability, test coverage, and test generation when designing a method for testing a digital system.

4. Describe different approaches for design for testability such as ad-hoc, full-scan/partial scan, built-in-self-test (BIST), etc.

5. Describe features/architecture of the JTAG standard and its role in digital systems testing.

6. Describe the role of computer-aided testing tools for digital systems testing .

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Reference:

1.  A Report in the Computing Curricula Series ,Joint Task Group on Computer Engineering Curricula, Association for Computing Machinery (ACM) , IEEE Computer Society, Version 2015 October 25 .