MEQ 1

Module Code: 3002 CEM

Module Title: Hardware Realisation of a Computer System

Date: 2018/19 Academic Year - Semester 1

Reflection on the student feedback:

This was the first time I delivered the 3002CEM module. The MEQ result shows that the overall student satisfaction for this module is 58.4%. Out of 12 students who contributed to the survey, 7 agreed that they are very much happy with the module delivery. Two students disagreed and three responded with a neutral answer (neither agree nor disagree) which is statistically considered as a negative answer.

Overall, the module was delivered well and students appreciated the effort put by the lecturer. The students also acknowledged the importance of the module for the course and for their professional career. However, students have mentioned the excessive content and slides in lecture notes. As a new lecturer at Coventry University, this was a new teaching experience for me as I was running the module for the first time. Some of the students were very weak who had issues to understand the content from the beginning. Whereas, it was moderately easy for others to follow the lecture notes. Based on the current year observation and experience, I will adjust the content of the module in the following year. More visual material will be used to simplify the complex processor architecture into parts.

In order to improve the overall satisfaction rate, following changes would be considered for the next academic year:

1. Reduce the content of the lecture slide.

2. More detailed lab sheet for VHDL and FPGA.

3. Start VHDL part of the module from the scratch. In addition, processor architecture part will be taught a bit earlier (week 4 or 5).

4. Recommend and follow a specific book and provide it for students through Flying start.

Long-term plan:

1. Teach 3001CEM module in the first semester and this module in the 2^nd semester. This will help students to understand the processor architecture and design first before implementing it using VHDL/FPGA.

Finally, I will wait for the final results to see how students perform in the module and adjust the plan accordingly.